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Registered: ‎10-24-2018

Availablity of bitstream for ZCU102 to enable Trace port via EMIO

Hi All,

We are using Xilinx Ultrascale+ ZYNQ-102 board and trying to enable trace interface via FPGA Fabric/PL (routed via EMIO to the MICTOR connector on the board) with Lauterbach.

Can you please let me know where I can get the complete Vivado Project including bitstream for the ZYNQ-102 board which has PL/PS trace facility enabled ? Also, I am trying to follow AR# 66669 for reference and can see the signals mentioned in trace.xdc but not sure how to configure them ? 

One more issue which I am facing is in enabling DBG_TRACE clock. I can see that option is not available in Clock Configuration under FDP System Debug Clock. Can you let us know, how to enable DBG_TRACE clock?

Refer me detailed instructions to get the trace via FPGA Fabric/PL from the Lauterbach if possible ?

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Xilinx Employee
Xilinx Employee
Registered: ‎10-11-2011

The Vivado IPI design is pretty simple.

Check box TRACE in the PS configuration wizard and make those TRACE connections external as showed in the AR.

Add the xdc file to the constraint and be sure the name match the top level signals name.

Other than that, Lauterbach website has the script to start talking to A53 and R5 once the system successfully booted (with the bitstream in it) from an SD card (for example).

Don’t forget to reply, kudo, and accept as solution.
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