04-17-2017 10:45 PM
The AXi Quad SPI for Zynq show the following erroneous behaviour in 8 bit slave mode:
After the master enables clock, the slave sends the first byte twice.
I could see this also on the Oscilloscope.
In 32 bit slave mode, the bytes are sent correctly.
Is that a known issue of the AXI Quad SPI ?
04-18-2017 07:02 AM
After a few experiments, I found out the following if you want to send two more bytes:
Before enabling the SPI system (via bit 1 of SPICR) , the Fifo must have already 2 entries.
Here is the sequence how the slave sends the correct bytes, when the master activates SS and Clock
Is this only a workaround or expected behaviour?
04-26-2017 08:40 AM
We have a problem similar to you. We are using SPI in slave mode (FIFO with 256 words of 32 bits), but we are using CDMAs. But the result is the same, sometimes the slave send the first word of 32 bits twice. And this only happens under certain clock configuration.
We checked the step you wrote in order to solve the problem but it did't work for us.
Do you know if this issue is a bug in the AXI Quad SPI v3.2? I've found that that this IP of Xilinx has other errors like this: https://www.xilinx.com/support/answers/68511.html but the error is only in master mode.
Do you know how to report this weird issue to xilinx?
05-10-2017 08:56 AM
Thank you very much in advance for your help.
I am sorry for answering so late, but right know a workmate is working in order to solve this issue, I told him that I've opened this ticket so if need some help he'll make contact with you trough this forum.
Thank you very much again.
07-03-2019 02:13 PM
Thanks for giving me that idea. Mine actually worked by just resetting the Tx by writing 0x20 instead of 0x60. I didn't have to put two entries in the FIFO before enabling it then fill the rest. Here's what I did:
1. XSpi_Transfer() for master
2. Set SPICR to 0x20 to clear Tx FIFO (don't want to clear receive data)
3. XSpi_Disable() slave
4. Fill FIFO
5. Enable the device