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Registered: ‎05-13-2019

BOOT.bin doesn't program pl

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Hello. I have an issue with programming pl on my zynq 7z020 (z-turn board). I do not have JTAG cable, but always do this by using BOOT.bin on sd card. There are two projects: one is something like a test for the other and their difference in the design is ip-block fifo generator. The first works great and does what needs to be done, the second doesn't do anything, does not even blink the led. I guess that something wrong with fsbl, what do I need to do?  Where find the information about configure fsbl?

Second project works great with another board programmed with JTAG by my colleague.

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466 Views
Registered: ‎05-13-2019

Sorry, i found what it was.Thanks for reply.

My design oriented to external clock and i just overworked. :)

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-14-2018

hi @hashhashhashhash 

1. Could you check and compare  the 2 bif files for generating BOOT.bin ?

2. You may want to turn on print info for FSBL by #define FSBL_DEBUG_INFO in fsbl_debug.h, to get more boot stage indications.

3. Is you boot mode pin correctly set to SD boot?

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Registered: ‎05-13-2019

1. How exactly to compare?)

2.I turned on more information about fsbl and as far as i can see fpga programmed 

root@localhost:~#
Xilinx First Stage Boot Loader
Release 2018.2  Jul 15 2019-10:51:01
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x000F6EC0
Data Word Len: 0x000F6EC0
Partition Word Len:0x000F6EC0
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD14B7E
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00000A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0
PCAP DMA DEST LEN 0xF8007024: 0x000F6EC0
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x00010C5B
Data Word Len: 0x00010C5B
Partition Word Len:0x00010C5B
Load Addr: 0x04000000
Exec Addr: 0x04000000
Partition Start: 0x000FD490
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xF7ED03ED
Application
Handoff Address: 0x04000000
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status = 0x1

But it not do its job. It must write to the memory samples from ADC and give interrupts to ps, but nor interrupts nor samples i can see. For indicating i put some signals on LED and it not blinking.

 

3. Of course. At least further linux loading is good.

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Xilinx Employee
Xilinx Employee
483 Views
Registered: ‎09-14-2018

@hashhashhashhash  已写:

1. How exactly to compare?)


Just open your BIF as a text file. below is an example: 

//arch = zynqmp; split = false; format = BIN
the_ROM_image:
{
[fsbl_config]a53_x64
[bootloader]***\fsbl.elf
[destination_cpu = a53-0, exception_level = el-1]***.elf
}

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Highlighted
467 Views
Registered: ‎05-13-2019

Sorry, i found what it was.Thanks for reply.

My design oriented to external clock and i just overworked. :)

View solution in original post

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