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willchenyx
Observer
Observer
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Registered: ‎12-18-2018

Can Ultrascale + MPSOC load and configure the PL before PS, or How to load and configure PL as soon as possible?

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AS our board is a PCIe endpoint, the PL must load and configure as soon as possible. If configure the PL until Kernel is loaded, its too late, the PC cannot recognise our PCIe endpoint(We run Linux on MPSOC).
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ritakur
Xilinx Employee
Xilinx Employee
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Registered: ‎09-01-2014

If you use Kernel to program PL, it won’t meet 100ms PCIe requirement.

You can use FSBL to program PL. it can meet 100ms.

The fastest boot device is QSPI, so you need to set SCLK to 150MHz and change XFSBL_PS_DDR flag in xfsbl_partition_load.c to skip loading bitstream to PL.

Here is the result we measured on ZCU106 using Tandem PROM bitstream with the change above.

You can see 1st stage Done only takes around 40ms, if you don't need to make 2nd stage under 100ms, only boot from QSPI at 150MHz is enough.

pcie.JPG

 

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ritakur
Xilinx Employee
Xilinx Employee
1,533 Views
Registered: ‎09-01-2014

If you use Kernel to program PL, it won’t meet 100ms PCIe requirement.

You can use FSBL to program PL. it can meet 100ms.

The fastest boot device is QSPI, so you need to set SCLK to 150MHz and change XFSBL_PS_DDR flag in xfsbl_partition_load.c to skip loading bitstream to PL.

Here is the result we measured on ZCU106 using Tandem PROM bitstream with the change above.

You can see 1st stage Done only takes around 40ms, if you don't need to make 2nd stage under 100ms, only boot from QSPI at 150MHz is enough.

pcie.JPG

 

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willchenyx
Observer
Observer
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Registered: ‎12-18-2018

Hi, Ritakur

Thanks for your reply!

One more question, how can I set SCLK to 150MHz?

The picture below is my setting of PS. Is that mean my  SCLK is 300MHz??(According to what i know, the usual frequency of SCLK is 100MHz)

搜狗截图20190628102926.png

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glena
Moderator
Moderator
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Registered: ‎03-19-2014

To set the QSPI device frequency, refer to AR69381

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willchenyx
Observer
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Registered: ‎12-18-2018

I replaced XQSPIPSU_CLK_PRESCALE_8 with XQSPIPSU_CLK_PRESCALE_2, just as AR69381 saied.
But after that the self-starting failed. I turn on the fsbl_debug_info, the message is
FlashID=0x0 0x0 0x0
XFSBL_ERROR_UNSUPPORTED_QSPI
I think it means FPGA cannot read back the spi flash id.
I also tried the way in Zynq_UltraScale_Boot_Time_3.1.xlsm which can be download at AR# 67475, also failed.

The following is the contents of the file:

The following fixes / changes must be applied to reproduce the results reflected in this spreadsheet

Vivado PCW defaults flash device to "Automatic" clocking mode, limiting it to 75MHz. Must use "Manual" clocking mode to achieve settings for 150MHz. FIXED in 2016.4

QSPI Devices Should be in QSPI/32 mode
Pre-FSBL Boot ROMs use register initializations (REG_INIT) to increase performance

(<= 2016.2) FSBL Mis-Reports Timing Information (CR 955837)
Edit xfsbl_main.c
replace XFsbl_Printf(DEBUG_PRINT_ALWAYS, "%d.%d ms.", (u32)tPerfMs, (u32)tPerfMsFrac);
with XFsbl_Printf(DEBUG_PRINT_ALWAYS, "%d ns", (u32)tPerfNs);

Peformance Mode for FSBL on Cortex-R5 requires TTC enabled
The FSBL on Cortex-R5 uses the TTC timers to perform its counts. These are not enabled by default. Ensure that you enable them in the Vivado hardware definition. Consult the TRM to determine which TTCs to enable and how to connect them. FIXED in 2017.2. TTC now enabled by default

(<= 2016.4) PCAP DMA Clock Source Must Be Changed From SYSOSC to PLL (CR 953521)
Edit xfsbl_hooks.c (to make this global add it to psu_init.c instead)
Add Xil_Out32(0xFFCA0004,0x1);
in function XFsbl_HookBeforeBSDownload()
immediately before return Status;

(<- 2016.4) FSBL Requires Additional Tap Delay Settings (CR 954261)
Edit psu_init.c
"Add /* Tap Delay Settings */
Xil_Out32(0xFF180390, 0x00000003U);
Xil_Out32(0xFF0F0138, 0x00000020U);
Xil_Out32(0xFF0F01F8, 0x00000000U);"
In function psu_init()
After the sequence of calls to psu_*_init_data()

(< 2016.4) FSBL Performance Mode Negatively Impacts Performance Due to Nested print() Calls (CR 955332)
do NOT use XFSBL_PERF to turn on performance mode
edit xfsbl_config.h
re-define FSBL_PERF_EXCLUDE_VAL to 0

(<= 2016.4) FSBL QSPI Driver Has Incorrect PRE-SCALER Value (CR 954261)
edit xfsbl_qspi.c
replace all instances of XQSPIPSU_CLK_PRESCALE_8
with XQSPIPSU_CLK_PRESCALE_2

 

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glena
Moderator
Moderator
1,279 Views
Registered: ‎03-19-2014

I suspect your QSPI cannot run at the frequency you are trying to set.    You can experiment with different QSPI REF Clocks in Vivado and divisors in xfsbl_qspi.c to determine the max frequency of your QSPI design.   A board simulation is another way to determine this.

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willchenyx
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Registered: ‎12-18-2018

I set the QSPI input clk with 300MHz, replaced XQSPIPSU_CLK_PRESCALE_8 with XQSPIPSU_CLK_PRESCALE_4, self_starting success, and can get 75M clk with OSC.

then set the QSPI input clk with 142MHz, replaced XQSPIPSU_CLK_PRESCALE_8 with XQSPIPSU_CLK_PRESCALE_2, self_starting fail, and can get 71M clk with OSC, but the duration is short between two 21Mhz durations, shown in the blow picture.

微信图片_20190722103837.jpg

 

We can conclude that QSPI can run at the frequency I am trying to set. If try to set XQSPIPSU_CLK_PRESCALE_2, something more MUST be needed.

 

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