cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
744 Views
Registered: ‎07-22-2018

Custom Zynq RFSoC board SD card boot not working

Hello,

I am trying to boot a custom board with Zynq Ultrascale+ RFSoC FPGA on it.  I have been able to boot a simple application, generated in Vivado 2018.3 and the Xilinx SDK, from QSPI on this board and am now trying to boot from the SD card using SD1-LS mode.  I followed the prepare boot medium procedure described in the following link for the 32GB SanDisk micro SD card:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841655/Prepare+Boot+Medium

I don't have a .bsp file for this custom board, so I used the petalinux 2018.3 zynqMP template when I created the project in petalinux.  I then referenced the .hdf file in the .sdk folder of the Vivado project when I ran petalinux-config.  I run petalinux-build and then petalinux-package with the default FSBL, PMUFW, ATF, and U-BOOT .elf files.  I mount the SD card and use cp to copy the BOOT.BIN and image.ub files to the FAT32 boot partition of the card.  I set the mode switch to SD1-LS on the FPGA board, insert the card and power up the board.  I see the PS_ERR LED go red.  I connect to UART0 using putty and push the SRST button on the board but see no output on the UART.  I have tried re-running the petalinux-package referencing the fsbl.elf file I created in the SDK which has FSBL_DEBUG_INFO defined in it, but get the same results.

I have searched online and seen a few people with similar issues that were caused by WP (write-protect) and CD (card-detect) polarity on their hardware.  From the schematic for my custom board, it appears that WP and CD are connected to the correct MIO and they have external pullup resistors.  Since WP and CD are not connected to the actual SD card connector, I'm not sure how these signals ever get pulled low.  The documentation on the level-shifter chip is very limited and it looks like the connections for the CD and WP ports simply have pull-up resistors inside it.

I have tried rebuilding the Vivado design without the CD and WP signals disabled, but have the same result.

I have tried slowing down the clock for the SDIO1 in the Vivado Zynq GUI, but have the same result.

Is there another way I can try to debug the SD1 interface without booting from it?  Maybe load some .elf file via JTAG and read some status registers or try to run the SD Init function?  Any suggestions are welcome.  Also, there are not any test points for the SD card interface, so it would be hard for me to check levels or for clock activity.

Also, I have tried a couple of other SD cards including the one that shipped with a ZCU104, but with the same results.

Thanks for any help!

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
660 Views
Registered: ‎10-11-2011

I suggest to open Vivado HW Manager, connect and dump the FPGA registers.

Two in particular should tell you why it's not booting:

JTAG_STATUS

JTAG_ERRRO_STATUS

Add them here and we can take a look at what the reason of the error might be.

NOTE: If you can boot from QSPI then your DDR should be fine. SD1 and SD1_LS are different methods. Are you sure you chose the correct one?

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos