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Contributor
Contributor
1,173 Views
Registered: ‎01-02-2015

Estimation for UltraScale+ RFSoC boot time and configuration

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Is there a tool or method for estimating the boot time of the Ultrascale+ RFSoC devices? I've seen AR# 67475, but the tool offered there does not appear to include the RFSoC devices.

 

EDIT: To clarify, I'm seeking the total time expected before the processor, pl, and rf section are all up and ready to do work.

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Moderator
Moderator
1,124 Views
Registered: ‎03-19-2014

the boot time estimates for RFSoC are the same as it has the same PS block as Zynq UltraScale MPSoC devices.   The AR will be edited to include the different bitstream sizes of the RFSoC product family

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Moderator
Moderator
1,125 Views
Registered: ‎03-19-2014

the boot time estimates for RFSoC are the same as it has the same PS block as Zynq UltraScale MPSoC devices.   The AR will be edited to include the different bitstream sizes of the RFSoC product family

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Contributor
Contributor
1,104 Views
Registered: ‎01-02-2015

So I can just change the bitstream size accordingly and expect to be in the ballpark? There's no extra time associated with setup of the ADCs and DACs?

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Contributor
Contributor
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Registered: ‎01-02-2015

I see that PG269 gives a power-up sequence for the RF Data Converter. Does this all take place in parallel with the bitstream configuration and other power-up operations of the FPGA? Or does it all happen afterward? Some of each?

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Xilinx Employee
Xilinx Employee
1,032 Views
Registered: ‎10-11-2011

I think there's some of each but nothing that would drastically improve you boot time.

The ADC and DAC can come up pretty much ready to go on bitstream programming.

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