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Observer martin6314
Observer
513 Views
Registered: ‎02-16-2018

Failing TSGEN timer access after FSBL authentication boot

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Hello,

 

Our design (ultrascale+, standalone, A53, SDK 2017.4) uses the timer TSGEN (master timestamp generator) for A53 load measurement.

 

On not authenticated boot, timer access is possible as expected:

  • TSGEN.CNTCR (0xfe900000) can be written and
  • TSGEN.CNTCVL (0xfe900008) can be read.

 

After authenticated boot, writing TSGEN.CNTCR causes the CPU to hang.

 

The register csu_status is 0 in the not authenticated case and 1 (authenticated) in the authenticated case, as expected. The image was built using

 

the_ROM_image:
{

 [pskfile] key\psk.txt

 [sskfile] key\ssk.txt

 [fsbl_config] bh_auth_enable

 [auth_params] ppk_select=0; spk_id=0x00000000

 [destination_cpu=a53-0,authentication=rsa,bootloader]FSBL.elf

 [destination_device=pl,authentication=rsa]Fpga.bit

 [destination_cpu=pmu,  authentication=rsa]PMU.elf

 [destination_cpu=a53-0,authentication=rsa]Core1.elf

 [destination_cpu=a53-1,authentication=rsa]Core2.elf
}

bootgen -image Test.bif -arch zynqmp -efuseppkbits key\pkhash.txt -w on -p XCZU2CG -o Test.bin

 

The UG1085 technical reference manual states that <<Software with sufficient privilege can read this counter.>>
So we assume a problem with the exception level of the Core.

This seems to indicate that we need to go the ARM trusted firmware route (ATF),
which seems to be a longer run and I wanted to avoid this as for now.

 

Can anyone explain me. If we want to use authentication:
1) Do we have to go the path of ATF and [trustzone,exception_level=el-3]
2) why access to TSGEN fails after FSBL authentication boot?

 

Thank you
Martin

 

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Xilinx Employee
Xilinx Employee
588 Views
Registered: ‎10-11-2011

Re: Failing TSGEN timer access after FSBL authentication boot

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I believe the TSGEN is a timestap in the debug coresight which is disable by default when booting securely.

Take a look at AR#68391

Some of those instruction should re-enable access to coresight components.

I don't know which one.

Denis

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2 Replies
Xilinx Employee
Xilinx Employee
589 Views
Registered: ‎10-11-2011

Re: Failing TSGEN timer access after FSBL authentication boot

Jump to solution

I believe the TSGEN is a timestap in the debug coresight which is disable by default when booting securely.

Take a look at AR#68391

Some of those instruction should re-enable access to coresight components.

I don't know which one.

Denis

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Observer martin6314
Observer
424 Views
Registered: ‎02-16-2018

Re: Failing TSGEN timer access after FSBL authentication boot

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Hi Denis

 

Thank you very much for your suggestion. As you mentioned, not all instructions are required to enable TSGEN. The following instruction is sufficient:

 

    Xil_Out32(0xFF5E0240,0x0);

 

Thanks again very much for this helpful information!

 

Martin

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