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Visitor
Visitor
555 Views
Registered: ‎05-30-2019

Is there a way for PL to load only encrypted bitstream?

FPGA:ZYNQ-7000

I set up eFuse through vivado:

企业微信截图_15638779519249.png

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I want pl to load only bitstream encrypted with my key in any case.

And now, I can still load unencrypted bitstream through uboot's "fpga load" command.But I don't want unencrypted bitstream to load.

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So, is there a way for pl to load only encrypted bitstream?

Or,is there a way I can make sure the bitstream going into the PL config module will always be sent to the AES/HMAC engine?

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Xilinx Employee
Xilinx Employee
504 Views
Registered: ‎10-11-2011

In zynq-7000, I am pretty sure you have to use RSA to force the partititon (in this case bitstream) to be encrypted.

Also, be sure to check this knwon issue: https://www.xilinx.com/support/answers/71437.html

In MPSoC the ENC_ONLY eFUSE actually enforce to have every single parititon encrypted.

 

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Highlighted
Visitor
Visitor
459 Views
Registered: ‎05-30-2019

Thank you for your reply.

Can this approach prevent unencrypted bitstream loading?

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Highlighted
452 Views
Registered: ‎07-23-2019

@xiyue5137

Correct me if I'm wrong, but my thought is that a bitstream is a sequence of bits, how does the PL figure out if it's encrypted or not? 

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Advisor
Advisor
436 Views
Registered: ‎04-26-2015


@archangel-lightworks wrote:

@xiyue5137

Correct me if I'm wrong, but my thought is that a bitstream is a sequence of bits, how does the PL figure out if it's encrypted or not? 


The bitstream is more than just the raw configuration bits; there's a fair bit of metadata too.

 

With that said, the goal is essentially to force the FPGA to decrypt every bitstream with the pre-programmed key. If the bitstream was not actually encrypted, or was encrypted with a different key, then the result will be a mess which will immediately fail the FPGA's own validity check - so it won't get loaded. The only way to get a functional design will be to give it a bitstream encrypted with the correct key, as intended.