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Newbie sinanakman
Newbie
4,378 Views
Registered: ‎07-21-2017

Re: JTAG Chain Configuration for Zynq UltraScale+ MPSoC

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Thanks for the follow up. Could you let me know how did you power them up ? Were you able to do this via the external debugger? At this point, we can't write to any debug registers. EDPRSR.SPD is stuck with 1 while EDPRSR.PU is zero.
Thanks
Sinan
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Visitor hefloryd
Visitor
3,173 Views
Registered: ‎03-01-2018

Re: JTAG Chain Configuration for Zynq UltraScale+ MPSoC

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We are trying to get OpenOCD running on the MPSoC ZCU102 board. It seems that some people in this thread have had success with third party JTAG probes, would you be able to share more details on the type of probe and how it was configured? 

 

Using OpenOCD we see a JTAG chain that looks similar to what was described in this thread previously (one TAP with ID 0x14738093 and another with ID 0). From this thread it seems that the JTAG_CTRL instruction needs to be issued, any ideas how to do that using OpenOCD?

 

 

 

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Visitor bensky
Visitor
2,373 Views
Registered: ‎07-03-2018

Re: JTAG Chain Configuration for Zynq UltraScale+ MPSoC

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Did you manage to get OpenOCD running with the ZCU102?

 

I always end up in the following:

 

Info : clock speed 1000 kHz
Info : JTAG tap: uscale.tap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : JTAG tap: uscale.ps tap/device found: 0x24738093 (mfg: 0x049 (Xilinx), part: 0x4738, ver: 0x2)
Info : JTAG tap: uscale.tap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : JTAG tap: uscale.ps tap/device found: 0x24738093 (mfg: 0x049 (Xilinx), part: 0x4738, ver: 0x2)
Error: JTAG-DP STICKY ERROR

> targets

    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
 0* uscale.a53.0       aarch64    little uscale.tap         unknown
 1  uscale.a53.1       aarch64    little uscale.tap         examine deferred
 2  uscale.a53.2       aarch64    little uscale.tap         examine deferred
 3  uscale.a53.3       aarch64    little uscale.tap         examine deferred

 

Which later will tell me always: "Target not examined yet" whenever I want to write something to the JTAG.

Thanks for any help!

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Visitor arvore
Visitor
408 Views
Registered: ‎09-21-2014

Re: JTAG Chain Configuration for Zynq UltraScale+ MPSoC

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I have an issue of not being alble to detect JTAG chan on Zynq UltraScale+ ZCU19EG FPGA. using DLC10 Xilinx dongle. It was detecting at some point yesrterday but then stop doing it. I've probed the flying leads singals seems to be fine, TDO is always high. I've varied the frequence of TCK to the lowest available 750000 Hz to no avial. Checked all voltages on board, all good. 

The total lengh of wires (including wires connected to JTAG pull ups on board plus flying lead of the dongle) would be around 10 inches or so. I am lacking the interface board allwoing me to uitilyze the JTAG header (placed on the other board, hence I am forced to connect with wires).

Yesterday, when the board worked, I could see correct device and SYSMON detected. Didn't see ARM core, but it could require progrmming the chain correctly to get to it as i understand it.

The chip was a bit warm, but not to the point it could get demaged I believe. I used the bench fan today to make sure itts stays cool but it never worked. 

 

Any ideas? 

 

Thank you in advance,

Ilya

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Newbie mumair
Newbie
348 Views
Registered: ‎11-05-2019

Re: JTAG Chain Configuration for Zynq UltraScale+ MPSoC

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Hi All,

I am trying to connect to Cortex-R5 core of Zynq UltraScale+ MPSoC using J-Link. I am using J-Link Commader software to establish connection. However I am facing an error which is attached below.

By reading this thread and working around the documentation (ug1085), I guess I need to write .JLinkScript to do propper configurations and hencr to get it working. Can you guys please refer to some helpful starting point.

Please look at following and guide me accordingly@pmg67 @pratham

J-Link>connect
Device "XCZU19EG_R5_0" selected.


Connecting to target via JTAG
ConfigTargetSettings() start
ConfigTargetSettings() end
InitTarget() start
Timeout while waiting for core to be halted after reset release
InitTarget() end
TotalIRLen = 16, IRPrint = 0x000411
JTAG chain detection found 2 devices:
 #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
 #1 Id: 0x14710093, IRLen: 11, Unknown device
AP map detection skipped. Manually configured AP map found.
AP[0]: CUSTOM-AP (IDR: Not set)
AP[1]: APB-AP (IDR: Not set)
AP[2]: CUSTOM-AP (IDR: Not set)
Using preconfigured AP[1] as APB-AP
AP[1]: APB-AP found
Found Cortex-R5 r1p3
8 code breakpoints, 8 data breakpoints
Debug architecture ARMv7.0
ConfigTargetSettings() start
ConfigTargetSettings() end
InitTarget() start
InitTarget() end
TotalIRLen = 16, IRPrint = 0x000411
JTAG chain detection found 2 devices:
 #0 Id: 0x00000001, IRLen: 05, Unknown device
 #1 Id: 0x14710093, IRLen: 11, Unknown device

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.
CPU-TAP not found in JTAG chain
ConfigTargetSettings() start
ConfigTargetSettings() end
InitTarget() start
InitTarget() end
TotalIRLen = 16, IRPrint = 0x000411
JTAG chain detection found 2 devices:
 #0 Id: 0x00000001, IRLen: 05, Unknown device
 #1 Id: 0x14710093, IRLen: 11, Unknown device
ConfigTargetSettings() start
ConfigTargetSettings() end
InitTarget() start
InitTarget() end
TotalIRLen = 16, IRPrint = 0x000411
JTAG chain detection found 2 devices:
 #0 Id: 0x00000001, IRLen: 05, Unknown device
 #1 Id: 0x14710093, IRLen: 11, Unknown device

****** Error: CPU-TAP not found in JTAG chain
temporarily halting CPU for reading CP15 registers.
CPU-TAP not found in JTAG chain
Cannot connect to target.

 

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