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Observer
Observer
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Registered: ‎02-20-2019

KC705 Boot from Quad SPI Flash

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This problem has been heavily covered in other posts, but I can't seem to find the cause of my problem.  

I am targeting a KC705 board with Vivado 2019.1 for an application which I would like to boot from DDR, after a first stage boot loader copies it from QSPI Flash to DDR.

I have created and SREC file with the application and programmed it, and the bit file image into QSPI Flash. 

It seems that when I run the boot loader via a JTAG connection, the boot loader successfully runs and copies the app from flash to DDR and then runs the app….no problem.

However, when I attempt to do a cold boot of the board, with/without jtag cable connected, the boot loader runs (I can see the status messages at my UART stdout terminal), but then hangs when it attempts to read the DeviceCode and ManufacturerID fields.  It reads back all FFs for each.  This reading is taking place in the Xilisf.c IntelStmFlashInitialize() function call.

This makes me think that there is perhaps something wrong in my block diagram or something else which is configuring the QSPI interface differently between the two boot scenarios, but I can’t really see what that could be, except maybe a difference in reset or clock timing between cold boot and JTAG boot.

I am clocking the Quad SPI ext_spi_clock at 10MHz and the Quad SPI axi_clock at 100MHz.  The rest of my system clocks at 200MHz.

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Observer
Observer
316 Views
Registered: ‎02-20-2019

Found the solution to my problem.  I checked "Enable Performance Mode" which enables the full AXI4 interface rather than AXI4-Lite.  What this offers according to the data sheet is " the AXI4 interface is used for burst transactions at the DTR and DRR locations".

Also, I corrected some reset network wiring errors in the design.  See attached pdf of the block diagram.

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Solution to reading Incorrect Manuf ID and dev code all FFs.JPG
Cold Boot From Flash.JPG
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1 Reply
Observer
Observer
317 Views
Registered: ‎02-20-2019

Found the solution to my problem.  I checked "Enable Performance Mode" which enables the full AXI4 interface rather than AXI4-Lite.  What this offers according to the data sheet is " the AXI4 interface is used for burst transactions at the DTR and DRR locations".

Also, I corrected some reset network wiring errors in the design.  See attached pdf of the block diagram.

View solution in original post

Solution to reading Incorrect Manuf ID and dev code all FFs.JPG
Cold Boot From Flash.JPG
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