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oscar717
Observer
Observer
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Registered: ‎02-26-2020

KU060 BPI Configuration Interface

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Hi,

I am trying to set up a BPI Interface between the KU060 and a NOR FLASH following the "UltraScale Architecture Configuration guide (UG570)". Also, I am using the AXI EMC IP to interface with the NOR FLASH. However, the very first issue that I encountered is that I am not able to select the Config Pins (D[03:00] in Bank 0) in the IO Planner. I have gone through Tools -> Device Properties -> Configuration Modes -> Selected "Master BPI-Up x8" but still not able to select these 4 pins. The for pins are labeled as: D00_MOSI_0, D01_DIN_0, D02_0, D03_0

Do you know how to select these 4 pins in the IO Planner, I need to assign them to the 4 LSB of the DQ NOR FLASH ?

See screenshot below:

Capture.PNG

 

 

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miker
Xilinx Employee
Xilinx Employee
866 Views
Registered: ‎11-30-2007

The pins [D00_MOSI_0, D01_DIN_0, D02_0, D03_0] are dedicated configuration pins and cannot be assigned.  You can reference the specific package file for your target device.  For example, the xcku060ffva1156 package listing below highlights these are not configurable pins but dedicated to the IO Bank 0 (Configuration Bank).

Device/Package xcku060ffva1156 3/22/2016 18:07:05                                                                                           
                                                                                                 
Pin   Pin Name                            Memory Byte Group  Bank  I/O Type  Super Logic Region  No-Connect
Y11   DXN                                 NA                 NA    NA        NA                  NA
U12   VCCADC                              NA                 NA    NA        NA                  NA
U11   GNDADC                              NA                 NA    NA        NA                  NA
Y12   DXP                                 NA                 NA    NA        NA                  NA
W12   VREFP                               NA                 NA    NA        NA                  NA
V11   VREFN                               NA                 NA    NA        NA                  NA
V12   VP                                  NA                 NA    NA        NA                  NA
W11   VN                                  NA                 NA    NA        NA                  NA
K7    M0_0                                NA                 0     CONFIG    NA                  NA
L7    M1_0                                NA                 0     CONFIG    NA                  NA
V7    INIT_B_0                            NA                 0     CONFIG    NA                  NA
M7    M2_0                                NA                 0     CONFIG    NA                  NA
W7    CFGBVS_0                            NA                 0     CONFIG    NA                  NA
R7    PUDC_B_0                            NA                 0     CONFIG    NA                  NA
P7    POR_OVERRIDE                        NA                 NA    NA        NA                  NA
N7    DONE_0                              NA                 0     CONFIG    NA                  NA
T7    PROGRAM_B_0                         NA                 0     CONFIG    NA                  NA
U9    TDO_0                               NA                 0     CONFIG    NA                  NA
V9    TDI_0                               NA                 0     CONFIG    NA                  NA
U7    RDWR_FCS_B_0                        NA                 0     CONFIG    NA                  NA
AA7   D02_0                               NA                 0     CONFIG    NA                  NA
AC7   D00_MOSI_0                          NA                 0     CONFIG    NA                  NA
Y7    D03_0                               NA                 0     CONFIG    NA                  NA
AB7   D01_DIN_0                           NA                 0     CONFIG    NA                  NA
W9    TMS_0                               NA                 0     CONFIG    NA                  NA
AA9   CCLK_0                              NA                 0     CONFIG    NA                  NA
AC9   TCK_0                               NA                 0     CONFIG    NA                  NA
AD7   VBATT                               NA                 NA    NA        NA                  NA

For post-configuration access to the parallel NOR flash via the dedicated pins, you can reference the following document which highlights the use of STARTUPE3:

  • UltraScale FPGA Post-Configuration Access of Parallel NOR Flash Memory using STARTUPE3 Application Note (XAPP1282; v1.0)

forums_startupe3.png

I hope you find this information useful.

Please Reply, Kudos, and Accept as Solution.

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miker
Xilinx Employee
Xilinx Employee
867 Views
Registered: ‎11-30-2007

The pins [D00_MOSI_0, D01_DIN_0, D02_0, D03_0] are dedicated configuration pins and cannot be assigned.  You can reference the specific package file for your target device.  For example, the xcku060ffva1156 package listing below highlights these are not configurable pins but dedicated to the IO Bank 0 (Configuration Bank).

Device/Package xcku060ffva1156 3/22/2016 18:07:05                                                                                           
                                                                                                 
Pin   Pin Name                            Memory Byte Group  Bank  I/O Type  Super Logic Region  No-Connect
Y11   DXN                                 NA                 NA    NA        NA                  NA
U12   VCCADC                              NA                 NA    NA        NA                  NA
U11   GNDADC                              NA                 NA    NA        NA                  NA
Y12   DXP                                 NA                 NA    NA        NA                  NA
W12   VREFP                               NA                 NA    NA        NA                  NA
V11   VREFN                               NA                 NA    NA        NA                  NA
V12   VP                                  NA                 NA    NA        NA                  NA
W11   VN                                  NA                 NA    NA        NA                  NA
K7    M0_0                                NA                 0     CONFIG    NA                  NA
L7    M1_0                                NA                 0     CONFIG    NA                  NA
V7    INIT_B_0                            NA                 0     CONFIG    NA                  NA
M7    M2_0                                NA                 0     CONFIG    NA                  NA
W7    CFGBVS_0                            NA                 0     CONFIG    NA                  NA
R7    PUDC_B_0                            NA                 0     CONFIG    NA                  NA
P7    POR_OVERRIDE                        NA                 NA    NA        NA                  NA
N7    DONE_0                              NA                 0     CONFIG    NA                  NA
T7    PROGRAM_B_0                         NA                 0     CONFIG    NA                  NA
U9    TDO_0                               NA                 0     CONFIG    NA                  NA
V9    TDI_0                               NA                 0     CONFIG    NA                  NA
U7    RDWR_FCS_B_0                        NA                 0     CONFIG    NA                  NA
AA7   D02_0                               NA                 0     CONFIG    NA                  NA
AC7   D00_MOSI_0                          NA                 0     CONFIG    NA                  NA
Y7    D03_0                               NA                 0     CONFIG    NA                  NA
AB7   D01_DIN_0                           NA                 0     CONFIG    NA                  NA
W9    TMS_0                               NA                 0     CONFIG    NA                  NA
AA9   CCLK_0                              NA                 0     CONFIG    NA                  NA
AC9   TCK_0                               NA                 0     CONFIG    NA                  NA
AD7   VBATT                               NA                 NA    NA        NA                  NA

For post-configuration access to the parallel NOR flash via the dedicated pins, you can reference the following document which highlights the use of STARTUPE3:

  • UltraScale FPGA Post-Configuration Access of Parallel NOR Flash Memory using STARTUPE3 Application Note (XAPP1282; v1.0)

forums_startupe3.png

I hope you find this information useful.

Please Reply, Kudos, and Accept as Solution.

View solution in original post

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oscar717
Observer
Observer
836 Views
Registered: ‎02-26-2020

Hi @miker ,

Yes, this useful information. I was missing the STARTUP3 primitive in the wrapper or top module. I still need to figure out how the STARTUP3 primitive works but at least I am closer to get it to work.

Thanks,

 

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