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Observer
Observer
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Registered: ‎07-09-2018

Loading PL in application works in debugger, fails in boot image

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Hello!

I am programming on a Zynq 7020. At the moment I am using a MicroZed, but have a custom system board I plan to move to. I am programming using Xilinx 2018.3.1 tools. I am attempting to build a QuadSPI boot image.

I have a very strict power-on timing requirement. For this reason, am having the FSBL load only the PS image. I am then using PcapLoadPartition() to load my PL image.

I did have to modify one line of the FSBL to prevent it trying to load my PL image.

 

image_mover.c, line 301:	while (PartitionNum < 2) {

 

 Normally it would go through all partitions loading them, but I only want it to load the FSBL and Partition 1, my PS.

 

I have all of this working in the debugger.

I can load my application through SDB and it runs fine. The PL is loaded and I can use it.

I created a boot image, however, and it appears to fail the moment I try to access the PL after loading. It loads the PL successfully. The FPGA Done light comes on. I execute a little bit of code after the load to show the application has not crashed, but as soon as I try to read a register from the PL the system hangs.

 

This does not happen when I run through the application in the debugger.

Further, after flashing the unit, I can run the FSBL through SDK and the application successfully loads from QSPI and runs to completion, using the PL I loaded in the application.

I tried slowing the system down by changing the Clock Ratio Mode register in ps7_init.c. The system ran more slowly, but crashed the same place.

I tried keeping the firmware load but commenting out the lines that access firmware registers. The program makes it to the end in this case.

I built my boot image using .elf files built in the Debug configuration. I don't feel like there should be a difference between executing the FSBL in SDK and executing it from the BootROM. Everything works in the Debugger.

I have also been using UART1 to send out serial messages using xil_printf for debugging and functionality checks. On the failed boot images most of these messages do not seem to show up. I don't know if this is related or a useful clue or what.

Does anyone have any ideas where else I should be looking to get this to work? Thank you.

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Moderator
Moderator
76 Views
Registered: ‎10-30-2017

Hi @limewater ,

Looks like the issue related to post config functionality in FSBL. If the PL bitstream is not loaded by FSBL then it will skip the post config code which is used to reserve the PL state before programming and restoring it after PL programmed. 

please add this post configuration functionality when you are loading bit stream and check. 

 

Best Regards,

Srikanth

 

 

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Moderator
Moderator
77 Views
Registered: ‎10-30-2017

Hi @limewater ,

Looks like the issue related to post config functionality in FSBL. If the PL bitstream is not loaded by FSBL then it will skip the post config code which is used to reserve the PL state before programming and restoring it after PL programmed. 

please add this post configuration functionality when you are loading bit stream and check. 

 

Best Regards,

Srikanth

 

 

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