I am using zynq UltraScale+ MPSoC device, and I am looking for a way for the PL logic to load the FW into the PS.APU CPU.
So the boot flow will be something like:
1. PMU+CSU standard flow
2. FSBL loaded into RPU
3. RPU is loading the PL bitstream
4. PL has some proprietary RTL that is reading the APU FW from external device.
5. The PL proprietary RTL is writing the code it read into the APU
6. The APU is released from reset and start booting/executing the code that the PL wrote to it at previous step.
So steps 1,2,3 and 4 can be done.
The question is if there is a way to implement 5 and 6.
Moving the code for APU from PL could be a simple transfer of data into a specific DDR location. That should be simple.
It's more complicated to release the APU and start the execution of such code.
I would recommend to look at the FSBL and see the necessary step to start the APU.
Maybe this steps can be executed by R5 rather than a master in the PL.