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Visitor
Visitor
1,584 Views
Registered: ‎04-23-2013

MPSoc, psu_init.c stay in a loop during DDR eye training

Hi, I have problems on custom board initialization.

Soft Version Vivado/SDK/petalinux 2017.4

Board version: custom board including a Zynq XCZU6EG

When I boot the board with JTAG flow (using psu_init.tcl) there is no problem

When I boot the board with FSBL flow, psu_init.c stay in a loop in psu_ddr_phybringup_data() :

regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/
while (regval != 0x80000FFF)
    regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/

readback value = 0x840007FF which means:

write eye training done = 0

read eye training error = 1

 

There are 2 chips MT40A512M16JY-083E on the board configure in vivado like following screenshot

ddr.png

If I comment the loop in the psu_init.c and create a linux from new FSBL I can boot on linux but it’s freezing after a while.

When I run memory test using JTAG flow (psu_init.tcl) all is pass except read eye training which freeze sometimes (not always).

I think there is problem in my DDR configuration but I don’t find it.

Do you have any ideas?

Thanks.

Tags (3)
ddr.png
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7 Replies
Xilinx Employee
Xilinx Employee
1,510 Views
Registered: ‎09-01-2014

DDR Configuration setting in PCW has less issue if it passed validation.

If the eye test didn’t pass, you would need to check your PCB.  

Do you meet PCB guideline from ug583?

Visitor
Visitor
1,416 Views
Registered: ‎08-01-2018

If your question was solved ,please tell us how to solve it!! Thank you very much!

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Visitor
Visitor
1,334 Views
Registered: ‎04-23-2013

we meet UG583 guideline.

For the moment it works with the modification of init.c : I changed the DDR configuration (use NO DM, NO DBI) and it seams to be better

But I'm not sure it safe !

Do you have any more suggestion ?

Thx,

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Explorer
Explorer
1,297 Views
Registered: ‎12-20-2017

Have you made any progress?  I am having a similar problem, and would like to hear how you resolved it.

 

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Visitor
Visitor
1,285 Views
Registered: ‎04-23-2013

No, not any progress for the moment !

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Xilinx Employee
Xilinx Employee
1,058 Views
Registered: ‎09-01-2014

This setting depends on your DDR connection.
if you don’t use the DM and DBI pin, you need use NO DM, NO DBI setting
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Visitor
Visitor
1,006 Views
Registered: ‎08-01-2018

You can try lastest version of the Vivado!

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