I am trying to follow this tutorial from Matlab to use Matlab as AXI master
https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/access-fpga-external-memory-using-matlab-as-axi-master.html
In stead of DDR3, I am just driving a slave register. When I generate bitstream, I receive the following issue and it is not programmed.
"there are no debug cores"
I am on xcku040 board and connecting to PC using USB-JTAG on board module. Any workaround? I am attaching my block diagram.