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Registered: ‎04-25-2017

Microblaze booting from a boot sequence residing BRAM


I am using Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit for my design. As you can see, I have put my whole design down here. I want to boot Microblaze from BRAM and nothing else(flash, SD card etc.) I am using BRAM with LMB controller. Also, I am open to AXI bus. I have tried every possible settings from AXI/LMB BRAM controller. The initialization of BRAM has issues. It gives random values and not correct ones from fed COE file.

  1. When using the primary method of populating the init files in the BRAM IP as .Coe file, a warning appeared which stated this
    [Memdata 28-122] data2mem failed with parsing error. check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components  initialization strings have not been updated.
    I have tried this and this in order to resolve the issue. When hardware was programmed with bit files ignoring the same, BRAM gave random data lines which were not fed through the Coe file. 
  2. I found from the data2mem guide that the bit file can be regenerated with data2mem by populating the BRAM independent of Vivado. The data2mem gave errors and I found out that it is no longer supported by Xilinx.
  3. I used updatemem which is the replacement for the dat2mem to generate the populated BRAM bit file. The bit file which was created, did not have any initialization of BRAM in form of .coe file. I used .mmi, .elf/.mem and .bit file in order to generate a new bit file which consists of BRAM initialization with updatemem.
  4. When I compared both the bit files, with and without the initialization of BRAM, BRAM from the hardware responded with zeros. Which clearly states that the BRAM is not properly populated.

Please check the block design, BRAM settings in screenshot and let me know where I am going wrong!

block design.png
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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎09-01-2014

If you use ZU+ MPSoc device, PS needs to boot first, it’s impossible to boot with Microblaze in PL.
I cannot find a ZynqMP IP in your BD, that’s why you see the errors.

Here is an example for MB ruining on Zu+ MPSOC device.
Xilinx Employee
Xilinx Employee
Registered: ‎10-11-2011

Thanks Taku!

The example only shows the JTAG boot flow but it's a good starting point.

I got it working from flash with an image created by this .bif.

Where hello_a53.elf is really a "stub" to park the processor and hello_my_mb.bin is the binary version of your MB application loaded in DDR. It's easier if MB application is in BRAM and that step is NOT required.

//arch = zynqmp; split = false; format = BIN




                [bootloader] fsbl.elf

                [destination_device = pl] design_1_wrapper.bit

                [destination_cpu = a53-0] hello_a53.elf

                [load = 0x0] hello_my_mb.bin


Don’t forget to reply, kudo, and accept as solution.
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