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Visitor oliver-fhg
Visitor
250 Views
Registered: ‎08-08-2019

Mode pins for JTAG debugging

Dear community,

I want to modify the device configuration of the FPGA XC7Z020 (CLG484) to be able to debug an application via JTAG. I am mainly wondering how to connect the Boot Mode Configuration pins (high/low) to do so. I've understood the following:

1) According to the "7 Series FPGAs Configuration User Guide" (UG470) there are there three dedicated mode input pins M[2:0]. For the JTAG configuration mode M[2:0] = 101 must hold.

2) According to the "Zync-7000 All Programmable SoC Technical Referenc Manual" (UG585) there are 7 boot mode strapping pins (MIO[8:2]). For the cascaded JTAG Boot Mode MIO[5:2] = 0000 must hold.  

3) According to UG585 there is a sclr BOOT_MODE register and BOOT_MODE[0/1/2/3/4] = MIO[5/3/4/2/6] holds.

 

I am still wondering about the following questions:

A) Which input pin M[2:0] corresponds to which MIO[8:2]?

B) From my perspective this information seems to be inconclusive. If the pins M[2:0] are a subset of MIO[5:2] it is impossible that both statements (1 and 2) are correct.

C) How can I experimentally determine the values of M[2:0] and MIO[5:2]?  When I use the Vivado Hardware Manager I can read out the following bits of the CONFIG_STATUS REGISTER:

REGISTER.CONFIG_STATUS.BIT08_MODE_PIN_M[0] 1
REGISTER.CONFIG_STATUS.BIT09_MODE_PIN_M[1] 1
REGISTER.CONFIG_STATUS.BIT10_MODE_PIN_M[2] 1

When I use the Vivado SDK I can read out the BOOT_MODE register (0xF800025C) but it only contains zeros. I cannot make sense of the different values. 

Any comment on the questions above or about Device Configuration Process in general will be greatly appreciated.

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3 Replies
Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎01-21-2013

Re: Mode pins for JTAG debugging

Hi @oliver-fhg,

 

UG470 is specific to the FPGA Configuration. Saying that, the M[2:0] are FPGA specific and for Zynq-7000 you should be concerned about the MIO[5:2], as described in Table 6-4 or UG585.

While some information may overlap between the two documents, for Zynq-7000 specific configuration information, please refer to UG585.

 


A) Which input pin M[2:0] corresponds to which MIO[8:2]?

     These are unrelated. The M[2:0] are related to the 7 series FPGAs and not the Zynq-7000 devices.

 

B) From my perspective this information seems to be inconclusive. If the pins M[2:0] are a subset of MIO[5:2] it is impossible that both statements (1 and 2) are correct.

     For 7 series FPGAs, M[2:0] = 101 must hold for JTAG mode.

     For Zynq-7000, MIO[5:2] = 0000 must hold for JTAG mode.

     

C) How can I experimentally determine the values of M[2:0] and MIO[5:2]? 

     You can read MIO[5:2] also from Vivado if you wished to continue some testing in Vivado.

     Check the JTAG_STATUS register BIT14_BOOT_MODE

     image1.png


In summary, I would recommend looking at UG585 for all Zynq-7000 Configuration related questions.

 

I hope this helps.

Thanks,
Wendy
Xilinx Technical Support
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Visitor oliver-fhg
Visitor
151 Views
Registered: ‎08-08-2019

Re: Mode pins for JTAG debugging

Dear Wendy,

thanks for the clarification. Yes, I would like to continue testing in Vivado. However, I cannot find an entry called JTAG_STATUS. These are all properties that I can read out of the device xc7z020_1: 

BSCAN_SWITCH_USER_MASK	0001
CLASS	hw_device
DID	jsn-DLC10-000015de5f6e01-23727093-0
FULL_PROBES.FILE	
IDCODE	00100011011100100111000010010011
IDCODE_HEX	23727093
INDEX	1
IR_LENGTH	6
IS_SYSMON_SUPPORTED	true
MASK	00001111111111111111111111111111
MASK_HEX	0FFFFFFF
NAME	xc7z020_1
PART	xc7z020
PARTIAL_PROBES.FILES	
PROBES.FILE	
PROGRAM.DPA_COUNT	0
PROGRAM.DPA_MODE	
PROGRAM.DPA_PROTECT	false
PROGRAM.FILE	S:/xxx/core_wrapper.bit
PROGRAM.HW_BITSTREAM	S:/yyy/core_wrapper.bit
PROGRAM.HW_CFGMEM	
PROGRAM.HW_CFGMEM_BITFILE	
PROGRAM.HW_CFGMEM_TYPE	
PROGRAM.IS_AES_PROGRAMMED	false
PROGRAM.IS_RSA_PROGRAMMED	false
PROGRAM.IS_SUPPORTED	true
PROGRAM.OPTIONS	
PROGRAM.READBACK_FILE	
REGISTER.BOOT_STATUS	00000000000000000000000000000001
REGISTER.BOOT_STATUS.BIT00_0_STATUS_VALID	1
REGISTER.BOOT_STATUS.BIT01_0_FALLBACK	0
REGISTER.BOOT_STATUS.BIT02_0_INTERNAL_PROG	0
REGISTER.BOOT_STATUS.BIT03_0_WATCHDOG_TIMEOUT_ERROR	0
REGISTER.BOOT_STATUS.BIT04_0_ID_ERROR	0
REGISTER.BOOT_STATUS.BIT05_0_CRC_ERROR	0
REGISTER.BOOT_STATUS.BIT06_0_WRAP_ERROR	0
REGISTER.BOOT_STATUS.BIT07_0_SECURITY_ERROR	0
REGISTER.BOOT_STATUS.BIT08_1_STATUS_VALID	0
REGISTER.BOOT_STATUS.BIT09_1_FALLBACK	0
REGISTER.BOOT_STATUS.BIT10_1_INTERNAL_PROG	0
REGISTER.BOOT_STATUS.BIT11_1_WATCHDOG_TIMEOUT_ERROR	0
REGISTER.BOOT_STATUS.BIT12_1_ID_ERROR	0
REGISTER.BOOT_STATUS.BIT13_1_CRC_ERROR	0
REGISTER.BOOT_STATUS.BIT14_1_WRAP_ERROR	0
REGISTER.BOOT_STATUS.BIT15_1_SECURITY_ERROR	0
REGISTER.BOOT_STATUS.BIT16_RESERVED	0000000000000000
REGISTER.CONFIG_STATUS	00000110000100000111111111111100
REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR	0
REGISTER.CONFIG_STATUS.BIT01_DECRYPTOR_ENABLE	0
REGISTER.CONFIG_STATUS.BIT02_PLL_LOCK_STATUS	1
REGISTER.CONFIG_STATUS.BIT03_DCI_MATCH_STATUS	1
REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS	1
REGISTER.CONFIG_STATUS.BIT05_GTS_CFG_B_STATUS	1
REGISTER.CONFIG_STATUS.BIT06_GWE_STATUS	1
REGISTER.CONFIG_STATUS.BIT07_GHIGH_STATUS	1
REGISTER.CONFIG_STATUS.BIT08_MODE_PIN_M[0]	1
REGISTER.CONFIG_STATUS.BIT09_MODE_PIN_M[1]	1
REGISTER.CONFIG_STATUS.BIT10_MODE_PIN_M[2]	1
REGISTER.CONFIG_STATUS.BIT11_INIT_B_INTERNAL_SIGNAL_STATUS	1
REGISTER.CONFIG_STATUS.BIT12_INIT_B_PIN	1
REGISTER.CONFIG_STATUS.BIT13_DONE_INTERNAL_SIGNAL_STATUS	1
REGISTER.CONFIG_STATUS.BIT14_DONE_PIN	1
REGISTER.CONFIG_STATUS.BIT15_IDCODE_ERROR	0
REGISTER.CONFIG_STATUS.BIT16_SECURITY_ERROR	0
REGISTER.CONFIG_STATUS.BIT17_SYSTEM_MONITOR_OVER-TEMP_ALARM_STATUS	0
REGISTER.CONFIG_STATUS.BIT18_CFG_STARTUP_STATE_MACHINE_PHASE	100
REGISTER.CONFIG_STATUS.BIT21_RESERVED	0000
REGISTER.CONFIG_STATUS.BIT25_CFG_BUS_WIDTH_DETECTION	11
REGISTER.CONFIG_STATUS.BIT27_HMAC_ERROR	0
REGISTER.CONFIG_STATUS.BIT28_PUDC_B_PIN	0
REGISTER.CONFIG_STATUS.BIT29_BAD_PACKET_ERROR	0
REGISTER.CONFIG_STATUS.BIT30_CFGBVS_PIN	0
REGISTER.CONFIG_STATUS.BIT31_RESERVED	0
REGISTER.COR0	02013fe5
REGISTER.COR0.BIT00_GWE_CYCLE	101
REGISTER.COR0.BIT03_GTS_CYCLE	100
REGISTER.COR0.BIT06_LOCK_CYCLE	111
REGISTER.COR0.BIT09_MATCH_CYCLE	111
REGISTER.COR0.BIT12_DONE_CYCLE	011
REGISTER.COR0.BIT15_SSCLKSRC	10
REGISTER.COR0.BIT17_OSCFSEL	000000
REGISTER.COR0.BIT23_SINGLE	0
REGISTER.COR0.BIT24_DRIVE_DONE	0
REGISTER.COR0.BIT25_DONE_PIPE	1
REGISTER.COR0.BIT26_RESERVED	0
REGISTER.COR0.BIT27_PWRDWN_STAT	0
REGISTER.COR0.BIT28_RESERVED	0000
REGISTER.COR1.BIT00_BPI_PAGE_SIZE	00
REGISTER.COR1.BIT02_BPI_1ST_READ_CYCLE	00
REGISTER.COR1.BIT04_RESERVED	0000
REGISTER.COR1.BIT08_RBCRC_EN	0
REGISTER.COR1.BIT09_RBCRC_NO_PIN	0
REGISTER.COR1.BIT10_RESERVED	00000
REGISTER.COR1.BIT15_RBCRC_ACTION	00
REGISTER.COR1.BIT17_PERSIST_DEASSERT_AT_DESYNC	0
REGISTER.COR1.BIT18_RESERVED	00000000000000
REGISTER.EFUSE.DNA_PORT	1041DC6037EF054
REGISTER.EFUSE.FUSE_CNTL	00C0
REGISTER.EFUSE.FUSE_DNA	2A0F7EC063B82083
REGISTER.EFUSE.FUSE_KEY	0000000000000000000000000000000000000000000000000000000000000000
REGISTER.EFUSE.FUSE_USER	00000000
REGISTER.IR	110101
REGISTER.IR.BIT0_ALWAYS_ONE	1
REGISTER.IR.BIT1_ALWAYS_ZERO	0
REGISTER.IR.BIT2_ISC_DONE	1
REGISTER.IR.BIT3_ISC_ENABLED	0
REGISTER.IR.BIT4_INIT_COMPLETE	1
REGISTER.IR.BIT5_DONE	1
REGISTER.TIMER	00000000
REGISTER.TIMER.BIT00_TIMER_VALUE	000000000000000000000000000000
REGISTER.TIMER.BIT30_TIMER_CFG_MON	0
REGISTER.TIMER.BIT31_TIMER_USR_MON	0
REGISTER.USERCODE	ffffffff
REGISTER.USR_ACCESS	00000000
REGISTER.WBSTAR	00000000
REGISTER.WBSTAR.BIT00_START_ADDR	00000000000000000000000000000
REGISTER.WBSTAR.BIT29_RS_TS_B	0
REGISTER.WBSTAR.BIT30_RS	00
UNKNOWN_DEVICE	false
USER_CHAIN_COUNT	4
VARIANT_NAME	
XSDB_USER_BSCAN	1,3

Do I have to set the MIO[5:2] correctly (in my case 0000) in order to read out this information correctly? I am using the Xilinx Plattform Cable USB II Debugger. 

 

Kind regards,

Oliver

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Xilinx Employee
Xilinx Employee
68 Views
Registered: ‎01-21-2013

Re: Mode pins for JTAG debugging

Hi @oliver-fhg,

 

I was looking in Vivado with a connection to a Zynq UltraScale+ MPSoC board.

I've just tested with a Zynq-7000 board in Vivado and it doesn't seem possible.

 

It seems the best option to read back the mode pins would be via SDK/XSCT as you previously described.

 

Thanks,
Wendy
Xilinx Technical Support
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