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Viking
Visitor
Visitor
405 Views
Registered: ‎02-10-2021

No reset_reason bit set by SWDT1 (FD4D0000)

 

Zynq ultrascale system.

The watchdog apparently works and we end up with reset as expected except no bit in the reset_reason register (0xFF5E0220) is set after the watchdog trigger reset, we read value 0. Reset by other sources like RESET_CTRL, ps_por and ps_srst will set bit in reset_reason register as expected.

SWDT1 configuration:

 

RegRead -b 0xFD4D0000
0x000001c3
RegRead -b 0xFD4D0004
0x000011e1

 

xilinx-pmu-fw/pmufw.tcl

configapp -app pmufw define-compiler-symbols ENABLE_RECOVERY
configapp -app pmufw define-compiler-symbols ENABLE_ESCALATION
configapp -app pmufw define-compiler-symbols ENABLE_RECOVERY_RESET_SYSTEM

I dont find anything in TRM about no reset reason bit to be expected by SWDT1.

We use Xilinx-2018.3/SDK

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3 Replies
abhinayp
Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎07-12-2018

Hi @Viking ,

 

Are you reading register through application? or directly from xsct console? Let me investigate more on this behavior looking at the previous known issues.

 

Best Regards
Abhinay PS
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Viking
Visitor
Visitor
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Registered: ‎02-10-2021

Thanks.

Above was read in QNX, same value read with U-Boot. Our other reset sources read reset_reason bit as expected.

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Viking
Visitor
Visitor
195 Views
Registered: ‎02-10-2021

Hi again @abhinayp 

If there is some more information that would be useful, or something I should test please let me know.

Have you used SWDT1 and read reset_reason register?

 

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