02-10-2021 02:00 AM - edited 02-10-2021 05:08 AM
Zynq ultrascale system.
The watchdog apparently works and we end up with reset as expected except no bit in the reset_reason register (0xFF5E0220) is set after the watchdog trigger reset, we read value 0. Reset by other sources like RESET_CTRL, ps_por and ps_srst will set bit in reset_reason register as expected.
RegRead -b 0xFD4D0000 0x000001c3 RegRead -b 0xFD4D0004 0x000011e1
configapp -app pmufw define-compiler-symbols ENABLE_RECOVERY configapp -app pmufw define-compiler-symbols ENABLE_ESCALATION configapp -app pmufw define-compiler-symbols ENABLE_RECOVERY_RESET_SYSTEM
I dont find anything in TRM about no reset reason bit to be expected by SWDT1.
We use Xilinx-2018.3/SDK
02-11-2021 12:01 PM
Hi @Viking ,
Are you reading register through application? or directly from xsct console? Let me investigate more on this behavior looking at the previous known issues.
02-16-2021 01:45 AM