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Observer erliangyun666
Observer
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Registered: ‎12-01-2018

PS Read PL Configuration through PCAP in ultrazed SOM

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Dear

I desinged a simple ip and would like to read the configuration bit from PL to PS through PCAP. I reffered the xfpga_readback_example_1 in baremetal not linux, but it does not work, whether it is because this "PMU-FW is not running, certain applications may not be supported" , are there any demos for this, thank you very much!

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Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎10-11-2011

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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How did get these numbers for XCZU3EG?

#define FRAMES 14964
#define WORDS_PER_FRAME 93
#define PAD_FRAMES 1

 

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Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎10-11-2011

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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The example should be working and I am pretty sure it doesn't require the PMUFW.

How are you running it? Booting from a flash (FSBL + example) or directly from JTAG (Debug As flow)?

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Observer erliangyun666
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Registered: ‎12-01-2018

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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Thank you very much!

I checked the FSBL + example and directly from JTAG, but they all failed. My board is XCZU3EG SOM instead of the zcu102 board. I changed the frames, and other paramters as follows:

#define FRAMES 14964
#define WORDS_PER_FRAME 93
#define PAD_FRAMES 1

except for this change, i didn't modify others in the xfpga_readback_example_1 demo. I confused almost two weeks without progress. Can you give me some suggestions. Thanks again.

Best wishes!

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Xilinx Employee
Xilinx Employee
225 Views
Registered: ‎10-11-2011

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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How did get these numbers for XCZU3EG?

#define FRAMES 14964
#define WORDS_PER_FRAME 93
#define PAD_FRAMES 1

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Observer erliangyun666
Observer
198 Views
Registered: ‎12-01-2018

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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ref.jpg

I refer this, is it correct?

Thanks a lot.

Best wishes!

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Xilinx Employee
Xilinx Employee
191 Views
Registered: ‎01-21-2013

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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Hi @erliangyun666,

 

You are correct on the FRAMES and WORD_PER_FRAMES.

May I ask why you changed the PAD_FRAMES from 25 to 1?

My understanding is that should remain at 25 but I can double check that for you. 

 

You mention that it's not working. Can you clarify what is not working?

  • Are you successfully able to readback but do not see the expected data readback? 
  • Or you can't even perform the readback?

 

Thanks,
Wendy
Xilinx Technical Support
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Observer erliangyun666
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Registered: ‎12-01-2018

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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Xilinx Zynq MP First Stage Boot Loader
Release 2019.2 Dec 9 2019 - 16:07:29
FPGA Configuration data Read back example
FPGA Configuration Read back Failed
FPGA Configuration Read back example Failed

It reports like this

Thank you, even though this time, i changed that to 25, it still reported failed

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Observer erliangyun666
Observer
166 Views
Registered: ‎12-01-2018

Re: PS Read PL Configuration through PCAP in ultrazed SOM

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In jtag and debug mode, when i comment out the following code in static u32 XFpga_GetPLConfigData(const XFpga *InstancePtr) in xilfpag_pcap.c

/*Status = XFpga_GetFirmwareState();

if (Status == XFPGA_FIRMWARE_STATE_UNKNOWN) {
Xfpga_Printf(XFPGA_DEBUG, "Error while reading configuration "
"data from FPGA\n\r");
Status = XFPGA_ERROR_PLSTATE_UNKNOWN;
goto END;
}

if (Status == XFPGA_FIRMWARE_STATE_SECURE) {
Xfpga_Printf(XFPGA_DEBUG, "Operation not permitted\n\r");
Status = XFPGA_FAILURE;
goto END;
}*/

it can read some byte and output like this

Xilinx Zynq MP First Stage Boot Loader
Release 2019.2 Dec 9 2019 - 16:07:29
PMU-FW is not running, certain applications may not be supported.
FPGA Configuration data Read back example
Bitstream contents are
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000

however, when i change it to SD mode, even though comment out the code, the output is like this

Xilinx Zynq MP First Stage Boot Loader
Release 2019.2 Dec 9 2019 - 16:07:29
FPGA Configuration data Read back example 

and after some while, it output

FPGA Configuration Read back Failed
FPGA Configuration Read back example Failed

I don't know how to solve it, can you give me some help

Thank you very much

Best wishes

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