Panic running ATF after FSBL

[borr]

Hi,

My team and I are trying to bring up a custom board running the Ultrascale+. We are building all images with the latest .hdf and .bit files for our board from Vivado 2017.4 using Yocto. When I try to use the jtag_boot.tcl script from http://www.wiki.xilinx.com/Booting+Zynq+UltraScale+Via+JTAG?responseToken=197255acc70ed6d35fc23316d726a3ba I can see that the PMU firmware and FSBL load and boot successfully. Then it seems that the ATF panics just after handoff from the FSBL. Here is the console log...

PMU Firmware 2017.3 Apr 5 2018 11:35:55

Xilinx Zynq MP First Stage Boot Loader

Release 2017.3 Apr 5 2018 - 11:34:15 NOTICE: ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000, wiPANIC at PC : 0x00000000fffea818

Is this a known issue with the FSBL -> ATF transition? Is there a simple configuration item that I'm missing when building either of the projects?

Regards,

Brian.

[gudishak]

Hi @borr,

Can you try booting changing the order of PMUFW then fsbl.elf instead of fsbl first and PMUFW?

Regards,

Kranthi

[borr]

Hi Kranthi,

Could you take a look at the jtag_boot.tcl script linked in my first post? I believe it does load (and run) the PMU firmware first before the FSBL. From what I can see the script does the following...

1. Load bitstream
2. Load PMU firmware
3. Run PMU firmware
4. Load FSBL
5. Run FSBL
6. Load U-boot
7. Load ARM trusted firmware (ATF)
8. Run ATF and U-boot
9. Load Linux kernel, devicetree, rootfs

Is there a different order I should try loading/running the binaries?

Regards,

Brian.

[glena]

You stated you're using 2017.4, but your PMUFW looks to be 2017.3.   Make sure all your code is from the same tool version.

[borr]

Thanks for the tip. I updated to Vivado 2017.4. Here is the boot error that follows...

Xilinx Zynq MP First Stage Boot Loader
Release 2017.4 Apr 11 2018 - 13:31:53
NOTICE: ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000, with PMU firmware
ERROR: BL31: No ATF handoff structure passedPANIC at PC : 0x00000000fffea818

This sounds very similar to the thread at (https://forums.xilinx.com/t5/Embedded-Linux/2016-3-ZynqMP-zcu102-Wrong-exception-level-in-ATF-BL31-after/td-p/730428) however I'm using the JTAG boot instead of generating a BOOT.bin. I will try setting one up and programming it to QSPI next. Any help getting the JTAG boot working would be greatly appreciated.

Regards,

Brian.

[glena]

Have you seen AR69153?   It shows a tcl script to download the FSBL, pmufw, uBoot, ATF, and a PL image.

[borr]

Quick update with a little more logging enabled...

Xilinx Zynq MP First Stage Boot Loader
Release 2017.4 Apr 11 2018 - 13:31:53
VERBOSE: Xilinx IDCODE 0x14730093
NOTICE: ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000, with PMU firmware
VERBOSE: Generic delay timer configured with mult=1 and div=100
ERROR: BL31: No ATF handoff structure passedPANIC at PC : 0x00000000fffeaaf4

[borr]

Thanks @glena, I hadn't seen your reply when I posted the update. I will give it a shot and come back with the outcome.

[borr]

Unfortunately I encountered the same error when running the script from the AR...

Xilinx Zynq MP First Stage Boot Loader
Release 2017.4 Apr 11 2018 - 13:31:53
VERBOSE: Xilinx IDCODE 0x14730093
NOTICE: ATF running on XCZU7EV/silicon v4/RTL5.1 at 0xfffea000, with PMU firmware
VERBOSE: Generic delay timer configured with mult=1 and div=100
ERROR: BL31: No ATF handoff structure passedPANIC at PC : 0x00000000fffeaaf4

Suggestions appreciated on how to proceed.

Regards,

Brian.

[borr]

Just to follow up in case anyone runs into a similar issue. I was able to work around the problem by making a debug build of the FSBL. Here is the patch from my build in 2018.1 ...

diff --git a/recipes-bsp/fsbl/fsbl_git.bb b/recipes-bsp/fsbl/fsbl_git.bb
index b9ec7e0..1fbb157 100644
--- a/recipes-bsp/fsbl/fsbl_git.bb
+++ b/recipes-bsp/fsbl/fsbl_git.bb
@@ -10,7 +10,9 @@ COMPATIBLE_MACHINE_zynqmp = "zynqmp"
 
 XSCTH_APP_COMPILER_FLAGS_append_zcu102-zynqmp = " -DXPS_BOARD_ZCU102"
 XSCTH_APP_COMPILER_FLAGS_append_zcu106-zynqmp = " -DXPS_BOARD_ZCU106"
-XSCTH_COMPILER_DEBUG_FLAGS = "-O2 -DFSBL_DEBUG_INFO"
+# XSCTH_COMPILER_DEBUG_FLAGS = "-O2 -DFSBL_DEBUG_INFO"
+XSCTH_COMPILER_DEBUG_FLAGS = "-O2 -DFSBL_DEBUG_INFO -DFSBL_DEBUG_DETAILED"
+XSCTH_BUILD_DEBUG = "1"
 
 XSCTH_APP_zynq   = "Zynq FSBL"
 XSCTH_APP_zynqmp = "Zynq MP FSBL"