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Observer
Observer
369 Views
Registered: ‎02-27-2020

Power up sequence of zynq ultrascale+

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Hi

I have question about the power up sequence of ZU7EV.

Basically,  I think vccint should be powered up first prior than other PL power rails.
Or I believe vccint/vccint_io/vccbram can be powered up at the same time if they are the same voltage.

 

Then, what happen if vccint is powered after vccbram?

I reached TI's solution that offers vccint is supplied after vccbram/vccint_io.
(Please see Figure 2 in following link)

https://www.ti.com/lit/ug/tiduep5a/tiduep5a.pdf

In this case, vccint is independent on the other 0.85V rail (vccbram/vccint_io) but vccint will be valid by power good from the vccbram/vccint_io power rail.

I appreciate If you have any information about this configuration and you can share.

 

BestRegards

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Xilinx Employee
Xilinx Employee
259 Views
Registered: ‎06-06-2018

Hi @u-sui ,

There is no cause for damage to device, unless all the power rails values are well within recommended operating voltage levels mentioned in data sheet.

Regards,
Deepak D N
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @u-sui ,

Please refer page 16 of DS925 (v1.17) for recommended power sequencing guidelines for MPSOC Devices.

 

Basically,  I think vccint should be powered up first prior than other PL power rails.
Or I believe vccint/vccint_io/vccbram can be powered up at the same time if they are the same voltage.

>>> Yes, you are correct.

 

Then, what happen if vccint is powered after vccbram?

>>> If you don't follow power sequencing also its fine. You might see more current consumption or Spikes at IO's at start and IO's will/may not be Tristate during power ON. But ensure you are well within Recommended voltage levels mentioned in the data sheet.

 

Hope this helps.

 

 

Regards,
Deepak D N
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Observer
Observer
270 Views
Registered: ‎02-27-2020

Hi Deepak 

Thank you for your reply.

I understood that if power sequence is not along with recommendation it leads to more current consumption or spikes at IO.

Could it be possible that the power sequence violation would lead to a damage of the device?

 

BestRegards

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Xilinx Employee
Xilinx Employee
260 Views
Registered: ‎06-06-2018

Hi @u-sui ,

There is no cause for damage to device, unless all the power rails values are well within recommended operating voltage levels mentioned in data sheet.

Regards,
Deepak D N
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Observer
Observer
244 Views
Registered: ‎02-27-2020

Hi Deepak

 

Thank you for your reply.

I understand.

 

BestRegards

u-sui

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