06-25-2019 03:31 AM - edited 06-25-2019 03:45 AM
For some reason, I need delay the powering on for certain bank (after my application code start running in PS side), so the bank must be powered on after the hardware bitstream has been written. But in UG585, it states:
The PL must be powered-up before it can be initialized and then configured with the bitstream.
So, anyone can confirm me for this?
06-26-2019 02:28 PM - edited 06-26-2019 02:30 PM
Configuration data for the PL-side of your Zynq7 is stored in SRAM-type internal latches, which are a form of volatile memory. That is, the PL-side together with the SRAM latches must be powered in order to receive and store the PL-side configuration data (see UG585, section 21.4).
Another important question is whether it is electrically safe to power-up the PS-side and the PL-side separately? The answer to this question is yes as described in the “PS-PL Power Sequencing” section of the Zynq7 datasheet (eg. Xilinx document DS187).
06-26-2019 11:07 PM - edited 06-26-2019 11:21 PM
Thanks for your reply.
I'm not very clear yet. In my situation, I can power up all other power rails follow the recommande power sequence without problem, but need delay the powering up of VCCO_34 . So the procedure is:
Power up -> write FSBL (bit stream) -> PS side application run -> (delay some time) -> power up VCCO_34
But before VCCO_34 powering up, the PL side runs already (I'm using other banks too, not only bank 34). From the datasheet, VCCO_x is the power supply for the output buffer, so what if the PL logic try to output high or low, or PS side try to access that bank (etc, by EMIO), when the output buffer isn't powered? Is it safe?
06-27-2019 04:33 AM
Thank you for clarifying the question.
As you know, VCCO is power for IO on the PL-side. So, as you note, the concern is with devices that talk to the PL-side.
Your power-up sequence is unusual and definitely not recommended.
Here is what I found about it being unsafe:
06-30-2019 08:02 PM - edited 06-30-2019 08:02 PM
Thanks for the relay again :). With the first clause:
My VCCAUX is 1.8V, and I can make it power up before the VCCO_x, sure it will power up before VCCO_34 (3.3V). I can't firgure out when their difference will exceed 2.625V.
07-01-2019 02:22 AM
If you turn OFF VCCAUX before you turn OFF VCCO_34 then difference will be greater than 2.625V and you could violate the TVCCO2VCCAUX specification.
What is part number for your FPGA?
Have you observed problems with IO in bank-34 on your board?
07-01-2019 07:26 PM - edited 07-01-2019 07:27 PM
My chip is XC7Z020. I designing the board power taking MicroZed board as a reference. But add TPS3106 to monitor the VCCPINT and VCCO_0. This will solve the problem of power up, and make PS eFUSE integrity, I think, according to AR#65240.
But it won't solve the power down sequece problem as you pointed out. So, any suggestions? Are there more elegant or integrated power solutions for Zynq7?
07-02-2019 05:02 AM
-good idea to look at Xilinx boards for ideas on powering the Zynq-7000 devices. I have not seen an integrated solution. Usually, a separate power IC is used for each needed voltage. Often, these power IC’s are chained together so they power-up in sequence rather than all at once.
If you are going to redo your board to solve the current VCCO_34 problem then follow “Power ON/OFF Sequencing” described in datasheet (DS187) for your XC7Z020. –and ensure that VCCO_34 comes up as recommended by DS187 for the PL-side supplies.