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sigifridus
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Registered: ‎06-28-2018

Problems to programm flash in cuctom board

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Hi everyone!
I have a problem with programming flash device in my custom board.

I use vivado 2019.1, zynq xc7z030, flash device spansion S25FL256

I have a project which i tested on zedboard and it is ok to programm flash.
but when i tried to programm flash in my new project i had folowing messages:

U-Boot 2019.01-07026-gae88108-dirty (Mar 22 2019 - 04:38:02 -0600)

 

Model: Zynq CSE QSPI Board

DRAM: 256 KiB

WARNING: Caches not enabled

In: dcc

Out: dcc

Err: dcc

Zynq> sf probe 0 0 0


Warning: SPI speed fallback to 100 kHz

SF: unrecognized JEDEC id bytes: 00, 00, 00

Failed to initialize SPI flash at 0:0 (error -2)

Zynq> ERROR: [Xicom 50-186] Error while detecting SPI flash device - unrecognized JEDEC id bytes: 00, 00, 00

Problem in running uboot
Flash programming initialization failed.

ERROR: Flash Operation Failed



i have found a AN98481 about read speed optimization. but i don`t understand what i must to do.
i have tried to change registers values in ps7_init.c, ps7_init_gpl.c, ps7_init.tcl according AN98481, but it didn't work.

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sigifridus
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Registered: ‎06-28-2018

I found accidental solution.
I added another fsbl to my project.
I have vivado 17.4 anl 19.1. the main vivado is 17.4. in the 19.1 i have tried launch my project.

when i have launched my project in sdk 17.4 i had this problem.

when i have launched my project in sdk 19.1 i had problem to running u-boot.

one moment i  tried to combine bootloader elf from 19.1 with my bit and elf project files in SDK 17.4. i created boot image consist this files.
after that i succesfuly programm flash.

View solution in original post

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abommera
Xilinx Employee
Xilinx Employee
1,867 Views
Registered: ‎10-12-2018

Hi @sigifridus ,

Please provide the log obtained by enabling the debug environmental variable  XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES can be set to 1 for debugging, see AR# 59272 for more details.

What is your boot mode settings used for programming, whether it is JTAG or QSPI? If it is QSPI, Can you please try with JTAG?

 

Thanks & Regards
Anil B
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sigifridus
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Registered: ‎06-28-2018

Thanks for your reply!
The boot mode is JTAG:
Screenshot_3.png


I change environmental variable  XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES

Screenshot_4.png

so where i can find a log? where i can see messages from u-boot?

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abommera
Xilinx Employee
Xilinx Employee
1,851 Views
Registered: ‎10-12-2018

Hi @sigifridus ,

Once close SDK project and re-open after setting the enviraonmetal variable. You can see the log in SDK console itself as you are observing now. Please share the full log of flash programming.

Thanks & Regards
Anil B
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sigifridus
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Registered: ‎06-28-2018

I have  changed environmental variable and restarted computer. 
Screenshot_6.png

I guess here I will see messages from u-boot or in the file SDK.log.

but i see nothing during programming. maybe i need set some another options in SDK or i do somthing wrong.

i am working in windows not in linux
thanks for answering!

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abommera
Xilinx Employee
Xilinx Employee
1,805 Views
Registered: ‎10-12-2018

Hi @sigifridus ,

Sorry I am not looking for sdk.log file. You have already provided this but share the full log once as below.

Flash_log.PNG

Thanks & Regards
Anil B
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sigifridus
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Registered: ‎06-28-2018

ok. I see this in console window during programming flash.

****** Xilinx Program Flash
****** Program Flash v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-DLC10-00001a33537001
Device 0: jsn-DLC10-00001a33537001-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA240 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA240
===== mrd->addr=0xF8000100, data=0x00033008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00033008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x000FA240 =====
READ: IO_PLL_CFG (0xF8000118) = 0x000FA240
===== mrd->addr=0xF8000108, data=0x0003C008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0003C008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B

 


U-Boot 2019.01-07026-gae88108-dirty (Mar 22 2019 - 04:38:02 -0600)

 

Model: Zynq CSE QSPI Board

DRAM: 256 KiB

WARNING: Caches not enabled

In: dcc

Out: dcc

Err: dcc

Zynq> sf probe 0 0 0


Warning: SPI speed fallback to 100 kHz

SF: unrecognized JEDEC id bytes: 00, 00, 00

Failed to initialize SPI flash at 0:0 (error -2)

Zynq> ERROR: [Xicom 50-186] Error while detecting SPI flash device - unrecognized JEDEC id bytes: 00, 00, 00

Problem in running uboot
Flash programming initialization failed.

ERROR: Flash Operation Failed

 

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abommera
Xilinx Employee
Xilinx Employee
1,764 Views
Registered: ‎10-12-2018

Hi @sigifridus ,

Have you configured QSPI correctly in PS from Vivado IPI. I believe there is an issue with PS settings in your design.

 

Thanks & Regards
Anil B
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sigifridus
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Registered: ‎06-28-2018

The problem maybe in vivado options or in scheme.

So where i can configure QSPI controller?
in zynq IP i can set MIO pins, QSPI ref clk.

i use same flash device as in zedboard. my starting project was target to zedboard. since i went to custom board, i have changed target part to xc7z030. i have changed PS clk and some pins. but i didn't change a control registers of qspi controller.

so what options i need to look?

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abommera
Xilinx Employee
Xilinx Employee
1,704 Views
Registered: ‎10-12-2018

Hi @sigifridus ,

Please make sure you are selecting correct flash configuration(sinlge or dual parallel) as per your hardware configuration.

Thanks & Regards
Anil B
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sigifridus
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Registered: ‎06-28-2018

I found accidental solution.
I added another fsbl to my project.
I have vivado 17.4 anl 19.1. the main vivado is 17.4. in the 19.1 i have tried launch my project.

when i have launched my project in sdk 17.4 i had this problem.

when i have launched my project in sdk 19.1 i had problem to running u-boot.

one moment i  tried to combine bootloader elf from 19.1 with my bit and elf project files in SDK 17.4. i created boot image consist this files.
after that i succesfuly programm flash.

View solution in original post

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