Programming BBRAM on Zynq-7000 based Arty Z7-20

[vijaykatoch]

Hello Everyone, 

I am trying to get Arty Z7-20 (Zynq-7000 XC7Z020) boot from flash with encryption enabled. I am following Xilinx 'XAPP1319' to program AES key to BBRAM.
I created MCS boot image with 'fsbl' and 'program_aes_key_bbram' application program(xilskey 6.3 example 'xilskey_bbram_example' for Zynq) for qspi flash as described in Xilinx 'XAPP1319'.

However on booting from SPI flash, BBRAM example print exit message 'BBRAM Example failed' on serial console. On debugging with JTAG, I found it fails while programming BBRAM, in function

Status = XilSKey_Bbram_Program(&InstancePtr);

The Arty Z7 is configured to boot in Cascaded JTAG mode. I suspect problem is the assignment of MIO pins in xilskey_input.h, in section related to definitions for BBRAM

/*
 * Definitions for BBRAM
 */
#define		XSK_BBRAM_MIO_JTAG_TDI	(17) /**< JTAG MIO pin for TDI */
#define		XSK_BBRAM_MIO_JTAG_TDO	(21) /**< JTAG MIO pin for TDO */
#define		XSK_BBRAM_MIO_JTAG_TCK	(19) /**< JTAG MIO pin for TCK */
#define		XSK_BBRAM_MIO_JTAG_TMS	(20) /**< JTAG MIO pin for TMS */
#define		XSK_BBRAM_MIO_JTAG_MUX_SELECT	(11) /*< JTAG MIO pin for MUX 			                                                     
                                                      selection line */                                                                                                                          

 
I don't know what it means by 'JTAG MIO pin for MUX selection line' ? How to configure it in HW?
Should JTAG not be used in cascaded mode and only for PL?
Anything else that need to be taken care of?

Thanks,

[glena · Accepted solution]

You are looking at the incorrect xapp, xapp1319 is for the Zynq UltraScale + MPSoC.  Instead look at Zynq 7000 documents XAPP1175, UG821, for the JTAG muxing, that is discussed in the xilsecure chapter of UG643.   The Security Hub for the Zynq 7000 can be found here