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Observer
Observer
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Registered: ‎10-09-2018

Programming QSPI flash failing

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Using SDK 2018.2 with a custom board built with Zynq-7000 (XC7Z020) and Cypress (Spansion) S25FL128S QSPI flash.

When I attempt to program flash (Xilinx --> Program Flash menu item), it fails:

cmd /C program_flash -f \
D:\Projects\Lam_Research\VIX_Probe_Interface\svn_repo-02\Firmware\ViX_App\bootimage\BOOT.bin \
-offset 0 -flash_type qspi_single -fsbl \
D:\Projects\Lam_Research\VIX_Probe_Interface\svn_repo-02\Firmware\ViX_FSBL\Debug\ViX_FSBL.elf \
-cable type xilinx_tcf url TCP:127.0.0.1:3121

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-HS3-210299A180FA
Device 0: jsn-JTAG-HS3-210299A180FA-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000001 =====
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
===== mrd->addr=0xF8007080, data=0x30800100 =====
===== mrd->addr=0xF8000B18, data=0x80000000 =====
Downloading FSBL...
Running FSBL...
Finished running FSBL.
READ: ARM_PLL_CFG (0xF8000110) = 0x30800100
READ: ARM_PLL_CTRL (0xF8000100) = 0x30800100
READ: ARM_CLK_CTRL (0xF8000120) = 0x00000000
READ: IO_PLL_CFG (0xF8000118) = 0x00000000
READ: IO_PLL_CTRL (0xF8000108) = 0x00000000
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0027DF0D
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x027E767B
Problem in running uboot
Flash programming initialization failed.

ERROR: Flash Operation Failed

With FSBL_DEBUG_INFO defined in the FSBL, the UART output shows:

Xilinx First Stage Boot Loader
Release 2018.2 Jul 16 2019-12:15:07
Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI
Single Flash Information
FlashID=0x1 0x20 0x18
SPANSION 128M Bits
QSPI is in single flash connection
QSPI is in 4-bit mode
QSPI Init Done
Flash Base Address: 0xFC000000
Reboot status register: 0x60502000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x88888888

I have defined XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES in my environment and restarted the SDK, there is no additional output on either the SDK console or the UART.

https://www.xilinx.com/support/answers/70148.html implies that the PLL/CLK info shown in the SDK console output may indicate a problem? We have reviewed the clock settings in the Vivado design and do not think anything is incorrect. In support of that, I am able to download and run the application through JTAG, including writing and reading pages in the QSPI flash memory.

In addition, I can connect the Digilent ARTYZ7 board that we used for early development before the custom board was built and programming flash there runs with no issues:

Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-Arty Z7-003017A70261A
Target 1 : jsn-JTAG-HS3-210299A180FA
Device 0: jsn-Arty Z7-003017A70261A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B

 


U-Boot 2018.01-00071-g0018654-dirty (May 01 2018 - 11:18:16 -0600)

 

Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Silicon: v3.1

DRAM: 256 KiB

WARNING: Caches not enabled

Using default environment

 

In: dcc

Out: dcc

Err: dcc

Zynq> sf probe 0 0 0


SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

...

 

Any suggestions on how to resolve this issue?
Thanks!
.Tim

 

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Highlighted
Observer
Observer
1,040 Views
Registered: ‎10-09-2018

Re: Programming QSPI flash failing

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As I was writing and posting this question, a colleague (@jott) was searching using a different string and was able to locate the answer in this post:  https://www.xilinx.com/support/answers/70548.html

Which in all of our previous searching had escaped us. We had an indication a separate FSBL was needed, but could not find the magic incantation till now.

View solution in original post

2 Replies
Highlighted
Observer
Observer
1,041 Views
Registered: ‎10-09-2018

Re: Programming QSPI flash failing

Jump to solution

As I was writing and posting this question, a colleague (@jott) was searching using a different string and was able to locate the answer in this post:  https://www.xilinx.com/support/answers/70548.html

Which in all of our previous searching had escaped us. We had an indication a separate FSBL was needed, but could not find the magic incantation till now.

View solution in original post

Observer
Observer
1,022 Views
Registered: ‎09-27-2017

Re: Programming QSPI flash failing

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Just to be clear we are programming a board were the boot mode is hardwired to QSPI Flash.

When Using the Prgram Flash tool you are asked to supply a FSBL. This FSBL needs to run in JTAG boot mode inorder to program the flash. Since the board is hardwired to QSPI an un modified FSBL won't work as it will read the boot mode and run in QSPI boot mode.

What AR70548 shows is how to create a modified FSBL that overwrites the QSPI Boot mode and sets it to JTAG mode so that the Flash programming works.

Out project now has two FSBLs one un modified which is used when generating the BOOT.bin and a modified one which is only used for programming the flash.

Our only concern now is to not get them mixed up when generating teh BOOT.bin :)

 

HTH

 

Jott