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Visitor
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Registered: ‎04-07-2020

QSPI speed / clock speed

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I'm designing a custom board using the XC7Z014S-CLG400 and am planning to boot from QSPI.  I'm using the Micron MT25QU128 at 1.8V in its 8-WPDFN package.  It specifies a clock frequency of 133MHz.

Looking at question 7 on https://www.xilinx.com/support/answers/59174.html, they talk about "QSPI_REF_CLK and QSPI_CLK on the CLK pin".  They also mention that "Remember that QSPI has two modes of operations depending on if the clock frequency is higher or lower than 40MHz.  Calculate and verify the QSPI clock speed"

When I look through user guides on how to configure the QSPI clock speed, I only find instructions on register settings, values I need to write to those registers, etc.  That sounds like things I would do at run time (i.e., after boot).  But I want to use the QSPI as the boot device.

Questions:

  • What are QSPI_REF_CLK and QSPI_CLK?  (as far as I can tell, the QSPI chip has just the one CLK pin)
  • What if my PS_CLK_500 is exactly 40MHz?  (I can still play with that, but currently, I'm using a 40MHz oscillator)
  • I know I have to configure MIO pins 8 to 2, as per Table 6-4 in the Zynq 700 TRM (UG585).   Do I need to "hard wire" anything to specify configuration settings related to the QSPI frequency?  (i.e., for the QSPI to be the boot device)

Thanks,
Cal-linux
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: QSPI speed / clock speed

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  • What are QSPI_REF_CLK and QSPI_CLK?  (as far as I can tell, the QSPI chip has just the one CLK pin)

QSPI_REF_CLK is the "input" to the  QSPI controller in zynq. QSPI_CLK is the clock on the interface (the pin). QSPI_REF_CLK is usually configured around 200MHz and QSPI_CLK is a divided down version. At boot the interface runs at ~13MHz and then can be speed up at run time under the proper conditions (follow PCB guidelines)

  • What if my PS_CLK_500 is exactly 40MHz?  (I can still play with that, but currently, I'm using a 40MHz oscillator)

The 40MHz refers to QSPI_CLK. Usually QSPI_CLK is either 25MHz or 50MHz or higher.

  • I know I have to configure MIO pins 8 to 2, as per Table 6-4 in the Zynq 700 TRM (UG585).   Do I need to "hard wire" anything to specify configuration settings related to the QSPI frequency?  (i.e., for the QSPI to be the boot device)

The PCB guidelines should have details. The MIO8 pin needs to be free to toggle. DO NOT load it with FET or LED. A simply pull-up or down is enough.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: QSPI speed / clock speed

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  • What are QSPI_REF_CLK and QSPI_CLK?  (as far as I can tell, the QSPI chip has just the one CLK pin)

QSPI_REF_CLK is the "input" to the  QSPI controller in zynq. QSPI_CLK is the clock on the interface (the pin). QSPI_REF_CLK is usually configured around 200MHz and QSPI_CLK is a divided down version. At boot the interface runs at ~13MHz and then can be speed up at run time under the proper conditions (follow PCB guidelines)

  • What if my PS_CLK_500 is exactly 40MHz?  (I can still play with that, but currently, I'm using a 40MHz oscillator)

The 40MHz refers to QSPI_CLK. Usually QSPI_CLK is either 25MHz or 50MHz or higher.

  • I know I have to configure MIO pins 8 to 2, as per Table 6-4 in the Zynq 700 TRM (UG585).   Do I need to "hard wire" anything to specify configuration settings related to the QSPI frequency?  (i.e., for the QSPI to be the boot device)

The PCB guidelines should have details. The MIO8 pin needs to be free to toggle. DO NOT load it with FET or LED. A simply pull-up or down is enough.

 

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Visitor
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Registered: ‎04-07-2020

Re: QSPI speed / clock speed

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Thanks Denist,

A quick follow-up question:

> QSPI_REF_CLK is usually configured around 200MHz and QSPI_CLK is a divided down version. At boot the interface runs at ~13MHz and then can be speed up at run time

So, for the purpose of booting from the QSPI (i.e., loading the FSBL into the on-chip memory), there's no issue with the clock frequency?

I'm just connecting the output of a 40MHz oscillator into PS_CLK_500  (the specs call for a frequency between 30MHz and 60MHz), and then connecting the four Data pins, CS, and SCLK from the Zynq to the QSPI flash memory chip.   Am I ok as far as the hardware design goes?

Thanks,
Carlos
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: QSPI speed / clock speed

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Yes. The clock "chain" will look like this:

PS_CLK -> IOPLL -> divided down to QSPI_REF_CLK -> divided down to QSPI_CLK (SCLK)

PS_CLK just need to be between 30 and 60 but it has nothing to do with the 40MHz limitation of the QSPI_CLK.

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