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peterjohn
Adventurer
Adventurer
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Registered: ‎10-18-2019

Re: Understanding PS_POR_B_500 in ZYNQ

I am using ZYNQ 7030. Therefore, I have looked in DS 191 instead of DS 187.

In DS191, section "PS Power-On/Off Power Supply Sequencing", it says that "The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity." 

Do we need to connect PS_POR_B to slide button and de-assert manually from ground when the voltages reach minimum level ? I don't think we have such buttons in the eval boards. Any suggestions how to implement it in smart way ?    

 

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jbeckwi
Xilinx Employee
Xilinx Employee
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Registered: ‎08-30-2011

Normally this signal is connected to a voltage monitoring circuit that can assert it when those power supplies have reached the desired levels.  Not a manual switch, but some sort of holdoff like a supervisor circuit or power monitoring IC.

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peterjohn
Adventurer
Adventurer
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Registered: ‎10-18-2019

@jbeckwi 

Is this signal "PS_POR_B" input or output ? How to assert this signal ? 

UG585 (v1.12.2) page 711 "The PS_POR_B reset pin is held Low until all PS power supplies are at their required voltage levels and PS_CLK is active"

This statement shows that this signal is asserted and de-asserted by the ZYNQ which means that it is an output signal, right ? 

How about not connecting this signal PS_POR_B in the custom board ?  

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derekm_
Voyager
Voyager
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Registered: ‎01-16-2019

It's an input; you absolutely shouldn't leave it disconnected as it is critical for the POR sequence. One thing you could do is look through the schematics of any Zynq platform to see what the reset circuit looks like. Often, the PS_POR_B signal is tied to the POWER_GOOD signal of the power distribution network (PDN). The PDN itself might contain a single power management IC with multiple (buck-converter) outputs, or there may be more than one IC. The PDN handles the power sequencing; the PS and PL supplies must come up in a defined manner for the Zynq to be initialized properly (have a look through UG933 for more details). Once all the supplies are up, the POWER_GOOD signal is asserted by the PDN, initiating the POR sequence (assuming POWER_GOOD is connected to PS_POR_B).

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