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Contributor
Contributor
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Registered: ‎12-23-2013

Reconfigure PL from PS in Bare-Metal system using devcfg driver

Hieveryone! Now I am verifying the function of reconfiguration PL from PS using devcfg driver in SDK.

The version of vivado is 2018.2, and the develop board is ZC706.

I want to run xdevcfg_polled_example.c in Bare-Metal system within SDK. After I review the code, I have some questions as below:

  1. The code check the status register to see whether it’s partial reconfigutaion. Before checking the status register, there were no steps to set partial reconfiguration or else. Is the application software’s responsibility to set?
  2. What is the format of configuration bitstream? .bit/.bin/.hex? I find some information on the internet, which says it must be .bin. How can I transform the .bit into .bin in SDK or vivado?
  3. The code has 2 macro defines: one is the bitstream location. What steps should I do to store the configuration bitstream into a pre-define location? Is there any example in Bare-Metal system?

Is there a integral document or code to demonstrate the process of reconfiguration PL from PS? Or must it be verified in Linux system?

Thank you for your reply, and I will quite appreciate it!

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: Reconfigure PL from PS in Bare-Metal system using devcfg driver

I beleive the user needs to indicate the bitstream is a partial.

Linux uses the .bin for sure. I would suggest you try that for xdevcfg as well.

Check AR#46913.

I suggest NOT to load the data using JTAG. I recall issues with that flow.

In my opinion you can load the bitstream.bin using the image (.bif) where the location is specified using the "load" attribute. See bootgen user guide for some examples.

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