09-15-2020 06:45 AM
TL;DR: I can program_flash the board, now how do I reboot the board after programming?
I have a build server that builds and flashes a ZynqMP board (specifically a Trenz TE0820 SoM 3cg_1e_2gb on a Trenz TE0703 carrier) using the Vivado 2018.3 utility program_flash, which works fine. But after the flashing, the board is in a limbo state, and I have to manually press the reset button on carrier board, after which the board boots up fine and starts application on APU0.
Is there an automated way to make the device reboot after program_flash has finished?
09-21-2020 02:36 PM
Since you are using program_flash, I assume you have JTAG connected, correct?
Using JTAG to reset the board may work for you. You can do that through the xsct program - use "conn" to connect, then "targ" to list targets. See what number the PSU is, then do "targ [number]" to select it. Finally, do "rst" to reset the processors, and you should see a print stating that one of the cores is at the reset catch - a "con" command will let it run.
09-22-2020 04:59 AM
This was also our first idea, however it does not seem to solve our problem.
I will try to elaborate but keep it short. We have two applications for apu0 and apu1, which writes a memory location, apu0 writes "cpu0 hello world" when there is a "0" in the mem-location, while cpu1 writes "cpu1 hello world" when there is a "1" in the location.
These applications is written to flash, together with a fsbl.elf, pmufw.elf, bitstream.bit, bl31.elf, uboot.elf, apu0.elf and apu1.elf. Here comes the problem as it kinda "hangs" waiting for a power-on-reset when flash is written with program_flash.
I think it should be a "rst -cores" instead of only "rst" based on the following
xsct% conn tcfchan#1 xsct% target 1 PS TAP 2 PMU 3 PL 4 PSU 5 RPU 6 Cortex-R5 #0 (Halted) 7 Cortex-R5 #1 (Lock Step Mode) 8 APU 9* Cortex-A53 #0 (External Debug Request, EL3(S)/A64) 10 Cortex-A53 #1 (Power On Reset) xsct% target 9 xsct% rst xsct% Info: Cortex-A53 #0 (target 9) Running (APU Reset) xsct% con Already running xsct% target 1 PS TAP 2 PMU 3 PL 4 PSU 5 RPU (Reset) 6 Cortex-R5 #0 (RPU Reset) 7 Cortex-R5 #1 (RPU Reset) 8 APU (L2 Cache Reset) 9* Cortex-A53 #0 (APU Reset) 10 Cortex-A53 #1 (APU Reset) xsct% rst -cores Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch) Info: Cortex-A53 #1 (target 10) Stopped at 0xffff0000 (Reset Catch) xsct% con Info: Cortex-A53 #0 (target 9) Running xsct% target 10 xsct% con Info: Cortex-A53 #1 (target 10) Running xsct%
Here it seems that the cores are running, but we do not see anything on the UART.
Either the cores are just reset, but nothing is initialized. It would be fine if it started all over, like a hard-reset.
I can manage to reset the APU if the application is already running, however this is not the case after a program_flash to QSPI. I actually tried to hack it, by writing to flash, and the use xsdk to put in a "reset-application" in DDR, and run that, but that did not work for me either, however i will play a bit more with this idea.
I hope this might clarify the issue.
09-22-2020 04:11 PM
Interesting - I tried my suggestion on a ZCU102 board booting from SD, but it is running just Linux on the 4 APU cores (no Cortex-R5 application). My setup is a little different it sounds like.
I also just realized that even if the CPU is reset, that doesn't re-start the warm boot process (involving the PMU and CSU) on Zynq ultrascale+, from what I understand. I believe the RESET_CTRL register can cause a system reset, it might be worth trying to write that over JTAG with the mwr command.
09-22-2020 11:46 PM - edited 09-22-2020 11:52 PM
I hope there exist some solution for this.
I tried the RESET_CTRL reg, address 0xFF5E0218 however i am not sure how to proceed from the following snippet. Before this, the QSPI was written by program_flash, hence in this limbo-state.
xsct% target 1 PS TAP 2 PMU 3 PL 4 PSU 5 RPU 6 Cortex-R5 #0 (Halted) 7 Cortex-R5 #1 (Lock Step Mode) 8 APU 9 Cortex-A53 #0 (External Debug Request, EL3(S)/A64) 10* Cortex-A53 #1 (Running) xsct% target 9 xsct% mrd 0xFF5E0218 FF5E0218: 00000000 xsct% mwr 0xFF5E0218 0x10 Memory write error at 0xFF5E0218. Invalid DAP IDCODE. Invalid DAP ACK value: 4 xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0xffff07dc (Cannot resume. Invalid DAP IDCODE. Invalid DAP ACK value: 0) xsct% Info: Cortex-A53 #0 (target 9) Running (APU Reset) xsct% target 1 PS TAP 2 PMU 3 PL 4 PSU 5 RPU (Reset) 6 Cortex-R5 #0 (RPU Reset) 7 Cortex-R5 #1 (RPU Reset) 8 APU (L2 Cache Reset) 9* Cortex-A53 #0 (APU Reset) 10 Cortex-A53 #1 (APU Reset) xsct%
I tried resetting them, but this gives the same result as before -> no output on UART.
xsct% target 9 xsct% rst -processor Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch) xsct% target 10 xsct% rst -processor Info: Cortex-A53 #1 (target 10) Stopped at 0xffff0000 (Reset Catch) xsct% target 10 xsct% con Info: Cortex-A53 #1 (target 10) Running xsct% target 9 xsct% con Info: Cortex-A53 #0 (target 9) Running
Again i think the system is not initialized, based on the program counter (PC)
xsct% rrd r0: N/A r1: N/A r2: N/A r3: N/A r4: N/A r5: N/A r6: N/A r7: N/A r8: N/A r9: N/A r10: N/A r11: N/A r12: N/A r13: N/A r14: N/A r15: N/A r16: N/A r17: N/A r18: N/A r19: N/A r20: N/A r21: N/A r22: N/A r23: N/A r24: N/A r25: N/A r26: N/A r27: N/A r28: N/A r29: N/A r30: N/A sp: N/A pc: 0000000000000200 cpsr: N/A vfp sys dbg acpu_gic
These are the same for both cores.
I tried running these psu_init etc, but maybe i did it wrong.
09-24-2020 03:50 PM
What boot mode is the board in after you reset? It looks like it failed to boot to me. My system is set for SD boot, which works fine after I write the reset register with JTAG or from Linux - the system starts booting from SD.
program_flash might also be doing something odd with the boot mode register. I'm tight on time right now, but I would need to run it myself and check the state of the system after a flash program.