So both myself and fpga engineer are new to this SOC and design flow.
I am having issue where I cannot run our image which I think it has something to do
with how we do pl-ps integration. Something is just not adding up for me and trying to
figure what we are doing wrong.
So the good news is that I am able to create own project,configure it and build. I am pointing to the official zcu102 bsp (2017.4) and official system*.hdf file. I end up with images in normal location. I create BOOT.BIN, copy on SD card. The eval board boots all of the way to the kernel prompt.
Now the bad, the fpga engineer created PL design. He exported it and gave me hdf file. I go thru the same process as above with exception of "configure" where I point to new hdf file. Now, the board does not boot.. halts early in the uboot.. Since I do not have PL as part of boot.bin, I do not think it is PL which causes it.
I am thinking that we have some sort of conflict between "petaLinux-create -s zcu102 bsp*" and our own hdf file.
Since hdf file is the only variable between the two, I am trying to understand why we are having conflicts and how to prevent them. Recommendations ?