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d_ortfeld97
Visitor
Visitor
496 Views
Registered: ‎03-07-2019

SD Boot is very slow - Set SD Card CLK frequency FSBL

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Hello,

We are facing some problems with our SD Interface on a custom board with Zynq Ultrascale+ MPSoC. The SD card runs at 3.3V with a Level-Shifter between the card and the Zynq. We used a SanDisk 16gb Class 10 UHS-I (https://www.xilinx.com/support/answers/66779.html).

After the Vivado Defaults for the SD1 Peripheral and the SDIO CLK (RPLL, 200MHz) did not work, we decided to use the IOPLL at 24MHz instead [20MHz and RPLL at 24/20MHz works too]. For more than 24MHz the boot failed.Vivado_SD1.png

Vivado_SDIO_CLK.png

FSBL, PMU Firmware and Demo Apps were created in Vitis. For all of them the Debug build is used. Watchdog is disabled in the FSBL. The bif looks as follows:

 

 

the_ROM_image:
{
     /* Partition for First Stage Bootloader */
     [bootloader,
     destination_cpu=a53-0] ./fsbl_02.elf

     /* Partition for PMU FW, loaded by FSBL */
     [destination_cpu=pmu] ./pmufw_02.elf

     /* Partition for Bitstream */
     [destination_device=pl] ./design_1_wrapper.bit

     /* Partition for Hello World for R5-0 */
     [destination_cpu=r5-0] ./hello_world_02_R5.elf

     /* Partition for Hello World for A53-0 */
     [destination_cpu=a53-0] ./hello_world_02.elf

}

 

 

Please find the attached result at boot. Everything is loaded properly, but overall it takes about 6 minutes! For some reason the CLK is running at ~44kHz (verified with measurement). It was expected to run at 24MHz, as set in Vivado.

This results in the following questions:

1. Why is the CLK frequency 44kHz, where does this frequency come from?

2. How can we set it to 24MHz correctly? Do we need to do this in the FSBL in Vitis? (Our target frequency is below 40MHz, as this is the maximum frequency of the Level-Shifter)

3. Is it possible that the problem is because of the bank voltage of 1.8V set in Vivado (first figure) and the real SD voltage of 3.3V? May this lead to the wrong speed mode?

Many thanks for any help in advance! Please let me know if some information is missing.

Daniel

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1 Solution

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denist
Xilinx Employee
Xilinx Employee
400 Views
Registered: ‎10-11-2011

The configuration in Vivado MUST be 200MHz. The clock gets divided down later by the driver itself.

1. Why is the CLK frequency 44kHz, where does this frequency come from?

This is the initialization phase of the card. It's expected and you should see communication over the CMD line.

2. How can we set it to 24MHz correctly? Do we need to do this in the FSBL in Vitis? (Our target frequency is below 40MHz, as this is the maximum frequency of the Level-Shifter)

In the driver itself. I believe there's an AR to help slow down the SD card speed.

3. Is it possible that the problem is because of the bank voltage of 1.8V set in Vivado (first figure) and the real SD voltage of 3.3V? May this lead to the wrong speed mode?

The SD card will always come up at 3.3V interface. If you are using the 1.8V bank for zynq AND there's no level shifters, that's a problem. More than the Vivado setting is important the bank power on the board.Is it 3.3V?

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3 Replies
denist
Xilinx Employee
Xilinx Employee
401 Views
Registered: ‎10-11-2011

The configuration in Vivado MUST be 200MHz. The clock gets divided down later by the driver itself.

1. Why is the CLK frequency 44kHz, where does this frequency come from?

This is the initialization phase of the card. It's expected and you should see communication over the CMD line.

2. How can we set it to 24MHz correctly? Do we need to do this in the FSBL in Vitis? (Our target frequency is below 40MHz, as this is the maximum frequency of the Level-Shifter)

In the driver itself. I believe there's an AR to help slow down the SD card speed.

3. Is it possible that the problem is because of the bank voltage of 1.8V set in Vivado (first figure) and the real SD voltage of 3.3V? May this lead to the wrong speed mode?

The SD card will always come up at 3.3V interface. If you are using the 1.8V bank for zynq AND there's no level shifters, that's a problem. More than the Vivado setting is important the bank power on the board.Is it 3.3V?

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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d_ortfeld97
Visitor
Visitor
346 Views
Registered: ‎03-07-2019

Thanks for the answer!
I think the mentioned AR is here https://www.xilinx.com/support/answers/69368.html

We will try that and let you know if it was succesfull.

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d_ortfeld97
Visitor
Visitor
297 Views
Registered: ‎03-07-2019

It turned out that we used wrong Pull-up Resistors on our board. Also we changed the Vivado Settings as follows: Pull Type: Disable, Speed: slowVivado_correct.PNG

Also we changed the Frequency for the SD Controller as suggested:

Vivado_SDIO_correct.PNG

We are now able to boot a simple program with bitstream from SD Card with 50MHz Clock Frequency (High Speed Mode) within half a second.

Many thanks for the support!

Daniel

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