05-21-2019 02:07 AM
My custom board design has a SD card 2.0 for booting the XCZU21DR SoC. As per SD card's general routing guidelines maximum trace length for the SD lines is to be 3000 mils to 4000 mils.
In our case we can not go below 6000 mils. As a solution to this :
1. Can I use a line driver/buffer gate for CLOCK line to compensate? Is this a good idea ?
2. Do I need to buffer all signals or just CLOCK will do?
05-21-2019 02:43 AM
You have two choices,
you can run on 'best parctice' or on simulation
personaly, I'd recomend you simulat the board, IBIS models are you friend here.
05-29-2019 10:28 AM
I agree on the IBIS models. Be sure there are no weird reflection on the zynq side of the SD clock. It's used to sample the data back and a reflection there can really messed up your sampling.