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Registered: ‎06-25-2016


Hi All,

I am using KC705 board.

We have successfully tested the UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 Primitive on the development kit as a feasibility test, but our actual platform is Kintex-7 FPGA (Not Ultrascale), So if i have to port the same design (xapp1280) to the Kintex-7 platform, i need to use STARTUP2 and not STARTUP3, as there is no support for the STARTUPE3 in kintex-7 FPGA.


When we tried to replace the STARTUPE3 with STARTUPE2, we are facing issues as there is no QSPI port in STARTUP2. So I requested you to share any design that we can refer for post-configuration Access of SPI-Memory using STARTUPE2.


I have attached screenshots for AXI_QUAD_SPI_IP GUI settings as well as block diagram connections.

I have some doubt regarding STARTUP_IO interface connections in the IP.

Please let me know if this interface has to be exported and if yes, how to connect this interface in my top module.

how do configure spi clock.

NOTE: i can use same application in 7series

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Xilinx Employee
Xilinx Employee
Registered: ‎01-21-2013


Hi sathamhussaina@iwavesystems.com,


In order to achieve a connection to external SPI slave from AXI Quad SPI in master mode, you are correct to enable the STARTUPE2 primitive and Master Mode.

I believe the IP internally connects SCK_O which is the SPI bus clock output to the USRCCLK0 pin of the STARTUPE2 primitive internally. You can check the code to view that.

Also, you can connect the CCLK pin to SCK of the external flash and this completes your connection.


We also have the following Design Advisory for using STARTUPE2 with AXI QUAD IP.


The AR describes in details how to constrain the STARTUPE2 primitive with respect to SCK and the MOSI and MISO signals.


Can you take a look at all of the above and let us know if you require further details or whether you experience any issues?


Xilinx Technical Support
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