cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
374 Views
Registered: ‎02-24-2020

Simulating ICAPE2 primitive on Vivado

I tried to simulate readback function of ICAPE2 primitive on Vivado and the device is XC7VX330TFFV1761. In the verilog source I set the SIM_CFG_FILE_NAME property as the generated RBT file. However, while simulating Vivado sent me a message that ICAPE2_inst has not finished initialization, and its initialization would never finish no matter how long the simulation time was. But when I set the SIM_CFG_FILE_NAME property of ICAPE2 to 'NONE', the initialization could finish at the time of 1254000 ps.

I wonder if there is any way to solve the problem. The verilog source is as follows (it is really simple).

module ICAPE2_RDBACK(
  input A,
  input [31:0] I,
  input CLK,
  input CSIB,
  input RDWRB,
  output [31:0] O,
  output B
);

  assign B = ~A;

// ICAPE2: Internal Configuration Access Port
// Virtex-7
// Xilinx HDL Language Template, version 2018.1

ICAPE2 #(
  .DEVICE_ID(32'h03667093), // Specifies the pre-programmed Device ID value to be used for simulation purposes.
  .ICAP_WIDTH("X32"), // Specifies the input and output data width.
  .SIM_CFG_FILE_NAME("F:/Vivado_project/ICAPE2/ICAPE2_RDBACK_1.rbt") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model.
)
ICAPE2_inst (
  .O(O), // 32-bit output: Configuration data output bus
  .CLK(CLK), // 1-bit input: Clock Input
  .CSIB(CSIB), // 1-bit input: Active-Low ICAP Enable
  .I(I), // 32-bit input: Configuration data input bus
  .RDWRB(RDWRB) // 1-bit input: Read/Write Select input
);

// End of ICAPE2_inst instantiation

endmodule

Tags (2)
0 Kudos
0 Replies