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davet
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Visitor
882 Views
Registered: ‎07-16-2020

Standalone application does not run without JTAG connected

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I have a standalone application developed with Vitis 2020.1 on a Zynq 7000 that runs as expected with the debugger. However, if I create a bootimage and program it into flash (QSPI boot), the application only runs IF a JTAG programmer is plugged in (I've tried both Platform Cable and SmartLynq).

I am using the auto generated FSBL that gets created with the Platform project in Vitis. The FSBL appears to work and does program the PL -- it just looks like the application doesn't start, like it may be in reset or have a stopped clock. However, as soon as I plug in the JTAG cable, the application starts running. I can remove the JTAG cable and it continues running. I've done some probing and saw there is activity on the JTAG lines without taking any action in Vitis, and I want to believe that the presence of the JTAG clock (or maybe other signals) is having an impact. None of the other signals from the Xilinx programmers are connected -- just vref and tms/tck/tdo/tdi.

Has anyone experienced this before or have any ideas? I'm starting to go down the path of digging into ps7_init.c, since that's one part of the boot process that least familiar with / most suspecting of.

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denist
Xilinx Employee
Xilinx Employee
768 Views
Registered: ‎10-11-2011

Do you have a UART? I saw this if the stdout in the BSP for the FSBL is set to "coresight" instead if UART or NONE.

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denist
Xilinx Employee
Xilinx Employee
769 Views
Registered: ‎10-11-2011

Do you have a UART? I saw this if the stdout in the BSP for the FSBL is set to "coresight" instead if UART or NONE.

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Steves_Job
Visitor
Visitor
462 Views
Registered: ‎05-07-2020

Did you find the the problem? I am having the same issue. Changing the stdout to none did not change the behavior.

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davet
Visitor
Visitor
450 Views
Registered: ‎07-16-2020

Changing stdout and stdin to UART/NONE did resolve this for me.

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jhouee
Observer
Observer
334 Views
Registered: ‎11-27-2015

,

Hello

I have the same issue but I didn't selected any UART in my design.

Where do you change  stdout and stdin to UART/NONE ?

Thanks

Johann

 

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boychantrau_9a4
Observer
Observer
311 Views
Registered: ‎03-30-2019

@jhouee  you can right click your fsbl_bsp -> board support package settings -> standalone -> there you can see stdout setting, change it to uart/none