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Visitor abibabi
Visitor
329 Views
Registered: ‎05-10-2018

US+ MPSoC configuration interface

we use XCZU5EV device (zynq US+ MPSoC)

 

at doc:

UG570 - UltraScale Architecture Configuration

 

written:

The configuration interface can operate only at 1.8V or 1.5V in the UltraScale+ FPGAs

 

 

- does it apply to the PL(programing logic) of the US+ MPSoC devices ?

- does it mean that in the PS_MIO bank were i connect the memory boot device (dual quad SPI @ bank500, MIO0-12) on my design

  i cant supply LVCMOS3.3v ?

- does it mean that bank PS 503 (dediceted config pins bank) allsow cant be supplied from 3.3V

 

TNX,

abi 

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1 Reply
Moderator
Moderator
270 Views
Registered: ‎03-19-2014

Re: US+ MPSoC configuration interface

ZU+ does not use the same PL configuration interface.  The PL is configured by the ARM via PCAP.   Refer to UG1085 chapter 11 for configuration and chapter 28 for the PS Multiplexed IO

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