02-19-2018 04:16 AM
We configure the PL of our UltraScale+ MPSoC from Linux command line (through FPGA Manager) using the following commands:
echo 0 > /sys/class/fpga_manager/fpga0/flags
echo design_1_wrapper.bit.bin > /sys/class/fpga_manager/fpga0/firmware
After the configuration the bitstream seems to be loaded correctly (the LEDs blink in the expected pattern an frequency for our bitstream) but registers connected to the PS by AXI are not accessible. If we try accessing them, linux hangs completely.
By "hangs completely" I mean the system is fully blocked. This is a strong contrast to other errors like accessing an inexistent register where we just get a bus error but the system continues running.
We also tried puttint the bitstream into the boot.bin so the PL gets configured by the FSBL. In this case everything works fine.
--> conclusion: The bitstream is working
If we re-configure the PL using FPGA Manager under Linux after the system booted correctly with the bitstream in the boot.bin, the AXI registers are inaccessible again.
1. Is this a known behavior?
2. Are there any workarounds?
02-20-2018 02:42 AM
The behaviour we see seems to match the following AR:
Unfortunately I could not really find out where I would have to place the files from the patch supplied with the AR to fix the issue in our linux environment. We built the linux using Yocto. Does anybody know where the files xilfpga_pcap.c/xilfpga_pcap.h are in the whole source code structure when building a Linux using Yocto?
02-23-2018 09:32 AM - edited 02-23-2018 09:39 AM
The file in question is part of xilfpga library and it can be found at:
I don't know how to patch it in the Yocto flow ... maybe a question for the Embedded Linux forum.