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Anonymous
Not applicable
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UltraScale+ ZCU102 INT_B and PS_ERR_OUT lights are red on power on

Hi all, I recently started developing on a ZCU102 board, and was able to program the FPGA just fine through the Xilinx SDK GUI (2018.3). However, today the INIT_B light has been stuck on red, even after power cycling multiple times. I was working on reading and writing data to the FPGA when I first noticed this.

 

This is a known issue for me, but for a while, I have not been able to program the FPGA through the SDK GUI, I get an error saying 

Program FPGA failed
  bitstream is not compatible with the target revision, use -no-revision-check to allow programming

Since I've known about this issue so I'm not concerned about it (unless it's relevant to the later problem).

 

So then I run the XSCT command:

xsct% fpga -no-revision-check C:/.../bitstream.bit

And I get the following:

initializing
xsct% fpga initialization failed

I've never seen this error before.

 

When I open Vivado, I get a warning from Auto Connect saying

 [Labtools 27-3421] xczu9_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal.

Both lights remain on throughout the process, and even after power cycles. Sometimes the PS_ERR_OUT light turns off after I run a debug instance. I would like to try wiping the flash, but I don't have a tool that will do that, and I'm not familiar with Vivado enough to know what I am doing.

 

Any ideas on what I can do?

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Moderator
Moderator
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Registered: ‎06-05-2013

Make sure you are using working image. If the mode pins are set to other than JTAG then try to set them to JTAG mode and load the design bit file and see if those LEDs goes off.

If it does then use the same bit file to create flash file and then share the results. Since this is our evaluation board, so you can use prebuilt images which can be found here https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0048-zcu102-evaluation-kit-hub.html 

From the revision check message it apprears that you are using ES2 board which is why tool is complaing about the rev mismatch. 

For erasing the flash you can follow the AR https://www.xilinx.com/support/answers/72140.html 

In Vivado/SDK, you will find this option in flash programming GUI. 

sas.JPGdad.JPG

Hope it helps.

Thanks

Harshit

 

 
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Anonymous
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As it turns out, we saw that the VCCBRAM and VCC3V3 leds were not on, so it looks like there is a power issue. I've seen another AR related to this that I will check out.
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Moderator
Moderator
1,041 Views
Registered: ‎06-05-2013

Try this one https://www.xilinx.com/support/answers/66811.html
VCCBRAM is 0x14 as per Maxim power rail
VCC3V3 is 0x17 as per Maxim power rail
Harshit
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Don’t forget to reply, kudo, and accept as solution.
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