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samual.mccallum
Observer
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Registered: ‎09-11-2019

UltraScale ZU11EG pre-boot sequence error on custom board

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Hello,

 

I am doing bring-up on a custom board for a ZU11EG MPSOC. I have established that there are errors occurring during the Pre-Boot Sequence preventing full boot (to Linux eventually), and I could use some assistance in identifying why they are occurring. Errors are almost guaranteed to be hardware related, and I am trying to identify what on my custom board would be causing them. The custom board is based off a functional reference eval design with minimal changes to critical parts of the system (i.e. power supply/sequencing, PS Bank 503 IOs, etc.).

I took the TCL script found at the bottom of AR#68659 and added additional register outputs as my debugging process moves along. See the register dump output at the bottom of the most recent output at power up (no PMU_FW or FSBL loaded). Register outputs are consistent power up to power up.

PMU_GLOBAL ERROR_STATUS_2 bit[25] and bit[24] are high, indicating a pre-boot sequence error as well as a PMU service request generating an error.

The PMU_LOCAL PMU_PB_ERR register value, 0x8200_0078 indicates a few different errors, but I am a bit unclear on how to interpret them. Some insight into their meaning would be appreciated.

In addition, the PMU_LOCAL PMU_SERV_ERR register value, 0x8000_0020, indicates a PL domain power supply failed. This may go hand-in-hand with the PMU_PB_ERR.

 

Any assistance in further debug steps, or interpretation of the above info, would be greatly appreciated.

 

Thank you,

Samual

 

TCL reg dump output:

======================================================================
==  Registers Dump
    IDCODE		                    = FFCA0040:   04740093
    PS_VERSION                      = FFCA0044:   00000513
    BOOT_MODE_USER                  = FF5E0200:   00000000
    BOOT_MODE_POR                   = FF5E0204:   00000000
    RESET_REASON                    = FF5E0220:   00000001
    PMU_IOMODULE.IRQ_PENDING        = FFD40034:   00000000
    PMU_GLOBAL.GLOBAL_CNTRL         = FFD80000:   00008800
    PMU_GLOBAL.MB_FAULT_STATUS      = FFD8052C:   00000000
    PMU_GLOBAL.MBIST_GOOD           = FFD80714:   00000000
    PMU_GLOBAL.PWR_STATE            = FFD80100:   00FFFCBF
    PWR_SUPPLY_STATUS               = FFD8010C:   00000007
    CSU_BR_ERROR                    = FFD80528:   00000000
    ERROR_STATUS_1                  = FFD80530:   00000000
    ERROR_STATUS_2                  = FFD80540:   03000000
    ERROR_SIG_MASK_2                = FFD8058C:   00001600
    PMU_LOCAL.PMU_PB_ERROR          = FFD60338:   82000078
    PMU_LOCAL.PMU_SERVICE_ERROR     = FFD6033C:   00800020
    csu_status                      = FFCA0000:   00000000
    csu_ft_status                   = FFCA0018:   00000000
    CSU_ISR                         = FFCA0020:   00008024
    pcap_status                     = FFCA3010:   80000A42
    tamper_status                   = FFCA5000:   00000000
    jtag_chain_status               = FFCA0034:   00000003
    jtag_sec                        = FFCA0038:   000001FF
    PS_SYSMON_STATUS_FLAG           = FFA508FC:   00000A00
    PL_SYSMON_STATUS_FLAG           = FFA50CFC:   00000000
    PL_SYSMON_STATUS_FLAG_1         = FFA50CF8:   00000200
  1  PS TAP
     2  PMU
        3* MicroBlaze PMU (Sleeping after reset. No clock)
     4  PL
  5  PSU
     6  RPU (Reset)
        7  Cortex-R5 #0 (RPU Reset)
        8  Cortex-R5 #1 (RPU Reset)
     9  APU
       10  Cortex-A53 #0 (Power On Reset)
       11  Cortex-A53 #1 (Power On Reset)
       12  Cortex-A53 #2 (Power On Reset)
       13  Cortex-A53 #3 (Power On Reset)
CONFIG STATUS: 310382348
                               CRC ERROR (Bits [0]): 0
                        DECRYPTOR ENABLE (Bits [1]): 0
                         PLL LOCK STATUS (Bits [2]): 1
                        DCI MATCH STATUS (Bits [3]): 1
             END OF STARTUP (EOS) STATUS (Bits [4]): 0
                        GTS_CFG_B STATUS (Bits [5]): 0
                              GWE STATUS (Bits [6]): 0
                            GHIGH STATUS (Bits [7]): 0
                           MODE PIN M[0] (Bits [8]): 1
                           MODE PIN M[1] (Bits [9]): 1
                          MODE PIN M[2] (Bits [10]): 1
          INIT_B INTERNAL SIGNAL STATUS (Bits [11]): 1
                             INIT_B PIN (Bits [12]): 0
            DONE INTERNAL SIGNAL STATUS (Bits [13]): 0
                               DONE PIN (Bits [14]): 0
                           IDCODE ERROR (Bits [15]): 0
                         SECURITY ERROR (Bits [16]): 0
  SYSTEM MONITOR OVER-TEMP ALARM STATUS (Bits [17]): 0
     CFG STARTUP STATE MACHINE PHASE (Bits [20:18]): 0
                     SECURITY_STATUS (Bits [23:21]): 4
                               RESERVED (Bits [24]): 0
             CFG BUS WIDTH DETECTION (Bits [26:25]): 1
                    SECURITY AUTH ERROR (Bits [27]): 0
                             PUDC_B PIN (Bits [28]): 1
                       BAD PACKET ERROR (Bits [29]): 0
                             CFGBVS PIN (Bits [30]): 0
                               RESERVED (Bits [31]): 0

 

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denist
Xilinx Employee
Xilinx Employee
546 Views
Registered: ‎10-11-2011

Lots of errors here:

PMU_LOCAL.PMU_PB_ERROR          = FFD60338:   82000078

0x00000008: SysMon Aux_Supply Check Error

0x00000010: SysMon IO_Supply Check Error

0x00000020: IOPLL Lock Error

0x00000040: DPLL Lock Error

0x02000000: FPD MBIST Zeroization Timeout Error

Check the power up with the scope and also PS_POR_B to get released after the power are steady.

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denist
Xilinx Employee
Xilinx Employee
547 Views
Registered: ‎10-11-2011

Lots of errors here:

PMU_LOCAL.PMU_PB_ERROR          = FFD60338:   82000078

0x00000008: SysMon Aux_Supply Check Error

0x00000010: SysMon IO_Supply Check Error

0x00000020: IOPLL Lock Error

0x00000040: DPLL Lock Error

0x02000000: FPD MBIST Zeroization Timeout Error

Check the power up with the scope and also PS_POR_B to get released after the power are steady.

-------------------------------------------------------------------------
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-------------------------------------------------------------------------

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samual.mccallum
Observer
Observer
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Registered: ‎09-11-2019

Thanks for the reply.

 

I'll have to think about a way to access the TPs for the power supplies, the mechanical structure of the board makes that a challenge at the moment.

In the mean time, I read a number of the SYSMON (PL/PS) voltage measurement registers, and I noticed VCCAUX reads as zero (same rail connects to VCCAUX_IO). This would likely explain the top two errors, and possibly the IOPLL/DPLL lock errors if they are not supplied with appropriate voltage.

Another interesting observation is that the VCCBRAM register reads as 0V and VCCINT as ~.87V (within tolerance), but they are connected to the same rail.

 

I will get back with power ramp up. My PS_POR_B status LED shows it is deasserted, but I will get back with relative timings.

 

Best,

Samual

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samual.mccallum
Observer
Observer
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Registered: ‎09-11-2019

The issue does seem to be related to the PS_POR_B deassertion time relative to the power supply ramp-ups. There is nearly zero delay from PS_POR_B being deasserted and the power supplies reaching steady-state. I believe TPSPOR is being violated and causing these errors to pop up.

On my reference board, I was able to simulate my custom board setup with the PS_POR_B signal and saw the exact same errors between the two boards down to a T.

I will go ahead and close this thread since I need to find a workaround. May be back if other errors pop-up.

 

Thanks very much for the quick response!

 

Regards,

-Samual

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