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Visitor
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Registered: ‎04-08-2011

Verification failed when programming QSPI with MPSoC US+ device via JTAG

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I am having issue with the QSPI Flash programming failing when doing verfication. I have a MPSoC UltraScale+ XCZU4CG FPGA. When programming the flash, the boot mode is in JTAG mode (mode 0000). The QSPI device is 2Gb Micron MT25 family flash device in Dual Parallel configuration (2 flash in parallel setup). My PS_Ref_Clk is 50MHz, Vivado version 2018.2. The flash programming via SDK and Vivado hardware manager indicates it failed verfication but "programmin" was sucessful. However, with a power cycle, the FPGA does not load the new image file. It seem to failed always at the same read data location (see below in red). Is there any way to see what is causing this issue. I am able to load the .bit file directly to the FPGA.

-----------------------------------------

sf write FFFC0000 780000 667C

 

 

device 0 offset 0x780000, size 0x667c

 

SF: 26236 bytes @ 0x780000 Written: OK

 

ZynqMP> Program Operation successful.

INFO: [Xicom 50-44] Elapsed time = 316 sec.

Performing Verify Operation...

0%...sf read FFFC0000 0 10000

 

 

device 0 offset 0x0, size 0x10000

 

SF: 65536 bytes @ 0x0 Read: OK

 

ZynqMP> cmp.b FFFC0000 FFFD0000 10000

 

 

byte at 0x00000000fffc0020 (0xaa) != byte at 0x00000000fffd0020 (0x66)

 

Total of 32 byte(s) were the same

 

ZynqMP> INFO: [Xicom 50-44] Elapsed time = 3 sec.

Verify Operation unsuccessful.

 

ERROR: Flash Operation Failed

 

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Visitor
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Registered: ‎04-08-2011

UPDATE: After upgrading to 2019.1 Vivado, we were able to program and verify our QSPI flash. 

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Visitor
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Registered: ‎04-08-2011

UPDATE: After upgrading to 2019.1 Vivado, we were able to program and verify our QSPI flash. 

View solution in original post

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