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Observer sheheeraismail
Observer
350 Views
Registered: ‎11-17-2017

Watchdog in freeRTOS vs bare-metal

Board used: picoZed board for Zynq7030 containing two ARM cores; cpu0 and cpu1.

I have a private APU watchdog in each cpu. cpu0 runs freeRTOS and cpu1 runs bare-metal. Each is hooked to its own interrupt controller, XScuGic.

The problem is... when cpu0 watchdog expires, it resets the system as expected; meaning... it internally resets SRST line (or POR line?) and is able to boot load in QSPI mode or SD mode. However, when cpu1 watchdog expires, the systems resets and then just... hangs. It does not load FSBL from QSPI or SD.

Is there some extra setting freeRTOS or FSBL perform regarding watchdog and reset? Does freeRTOS do software reset (SRST) different from bare-metal?

vTaskStartScheduler();
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4 Replies
Xilinx Employee
Xilinx Employee
328 Views
Registered: ‎10-11-2011

Re: Watchdog in freeRTOS vs bare-metal

" The CPU PrivateWatchDogs can optionally reset the whole chip. "

Maybe the settings for CPU1 WDT are not enabling the SRST?

Check UG585 Table 26.3 for a summary of reset effects.

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Observer sheheeraismail
Observer
297 Views
Registered: ‎11-17-2017

Re: Watchdog in freeRTOS vs bare-metal

In stand-alone application, i write over slcr registers so that it allows SRST and not just the CPU reset. 

#include <xil_misc_psreset_api.h>
#define A9_RS_AWDT_CTRL	(XSLCR_BASEADDR + 0x24C)
#define XSLCR_LOCK_ADDR (XSLCR_BASEADDR + 0x4)
#define XSLCR_LOCK_CODE 0x0000767B
void PrivateWatchdog_init()
{
int Status = XST_SUCCESS;
u8 Priority, Trigger;
XScuWdt_Config *WdtConfigPtr;
WdtConfigPtr = XScuWdt_LookupConfig(WatchdogDeviceId);
Status = XScuWdt_CfgInitialize(WdtPtr, WdtConfigPtr,
			WdtConfigPtr->BaseAddr);

	//--------if watchdog mode----------
XScuWdt_SetWdMode(WdtPtr);
XScuWdt_LoadWdt(WdtPtr, WDT_LOAD_VALUE);

Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
// RS_AWDT_CTRL for SRST
Xil_Out32(A9_RS_AWDT_CTRL, 0); //1 = CPU0, 2 = CPU1, 0 = system-level
Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE);//lock the slcr
}

After this I enable interrupt controller

XScuGic_Config *IntcConfig;
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
Status = XScuGic_CfgInitialize(&IntrCntrl, IntcConfig,IntcConfig->CpuBaseAddress);
if(Status != XST_SUCCESS)
		xil_printf("\nInterrupt controller not initialised");

//connect Intr controller's intr-handler to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
		(Xil_ExceptionHandler) XScuGic_InterruptHandler, &IntrCntrl);
….
….
//initialise and locally enable relevant peripherals
PrivateWatchdog_init();
// Enable exceptions in the Processor after all peripherals are connected
Xil_ExceptionEnable();
//now start the watchdog. When it expires, the debug breakpoint should go back to start of the program (Flash is read and bootROM loaded the code)
XScuWdt_RestartWdt(&WatchDogTimer);
XScuWdt_Start(&WatchDogTimer);

But no success. can you spot anything missing?

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Observer sheheeraismail
Observer
294 Views
Registered: ‎11-17-2017

Re: Watchdog in freeRTOS vs bare-metal

My code above has worked for me. Even though the default value for SLCR-> A9_RS_AWDT_CTRL is 0 (as visible from Memory Monitor of SDK), Writing 0 to it during _init() process makes it to behave as desired.

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Xilinx Employee
Xilinx Employee
281 Views
Registered: ‎10-11-2011

Re: Watchdog in freeRTOS vs bare-metal

Sorry but I couldn't spot anything wrong with what you are doing.

Do you think the system hangs because the WDT actually issued a SRST? You could attach the JTAG cable and try to read some REBOOT registers to identify any reboot errors or reboot reason.

 

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