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Registered: ‎04-07-2020

What is "FB CK" in TRM's Table 2-4 (MIO-at-a-glance)?

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Pin MIO8 is supposed to be pulled-up or down through a 20kΩ resistor to determine the bank's VCC voltage level;  the text in the PCB design guide warns that  "MIO[8] is a dual use pin that is shared with the high-speed QSPI/NAND/SRAM interface signals. Special care needs to be taken to avoid signal integrity issues."

When I look at Table 2-4 in the TRM, I see this:

Notice that the "fb ck" signal is clearly not in the context of "Quad SPI 0"  (as suggested by the thick lines).

I can't find any other mention of this "fb ck" signal, and I can't find any evidence supporting the above claim  (at least for the QSPI part — I don't see how MIO[8] is used for the high-speed QSPI interface)

Can someone shed some light on this?

Thanks,
Cal-linux
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Registered: ‎01-22-2015

Re: What is "FB CK" in TRM's Table 2-4 (MIO-at-a-glance)?

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@Cal-linux 

The most important use of MIO[8] (and MIO[7]) is shown on pages 56-57 of UG933(v1.13.1).  That is, these pins are strapped through 20K resistors to either GND or VCCO_MIOx and are indicators during boot-up of the range for voltages applied to VCCO_MIO0 and VCCO_MIO1.  As the caution says on page 57 of UG933, if these pins are not strapped correctly then damage may occur.

Page 58 of UG933 emphasizes that board traces from MIO[7] and MIO[8] to the strapping resistors must be short (<10mm).

On the Xilinx ZC706 board, I find that MIO[7] and MIO[8] are strapped as described above.

Page 358 and page 364 of UG585(v1.12.2) show that after serving its purpose as a voltage range indicator, MIO[8] can be used as part of a feedback clock for a fast (>40MHz) Quad-SPI interface.  This feedback clock is not described in detail by UG585.  However, for proper operation of the feedback clock, page 358 says "The feedback signal is received from the internal input from the I/O so MIO pin 8 needs to be programmed and allowed to freely toggle."  AR#51063 also talks about this feedback clock and MIO[8].

Cheers,
Mark

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Registered: ‎04-07-2020

Re: What is "FB CK" in TRM's Table 2-4 (MIO-at-a-glance)?

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When composing the message, I copy-n-pasted an image from screen capture, and the image showed.  But not in the post.

This is what I intended to show:

MIO-at-a-glance.png

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Registered: ‎01-22-2015

Re: What is "FB CK" in TRM's Table 2-4 (MIO-at-a-glance)?

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@Cal-linux 

The most important use of MIO[8] (and MIO[7]) is shown on pages 56-57 of UG933(v1.13.1).  That is, these pins are strapped through 20K resistors to either GND or VCCO_MIOx and are indicators during boot-up of the range for voltages applied to VCCO_MIO0 and VCCO_MIO1.  As the caution says on page 57 of UG933, if these pins are not strapped correctly then damage may occur.

Page 58 of UG933 emphasizes that board traces from MIO[7] and MIO[8] to the strapping resistors must be short (<10mm).

On the Xilinx ZC706 board, I find that MIO[7] and MIO[8] are strapped as described above.

Page 358 and page 364 of UG585(v1.12.2) show that after serving its purpose as a voltage range indicator, MIO[8] can be used as part of a feedback clock for a fast (>40MHz) Quad-SPI interface.  This feedback clock is not described in detail by UG585.  However, for proper operation of the feedback clock, page 358 says "The feedback signal is received from the internal input from the I/O so MIO pin 8 needs to be programmed and allowed to freely toggle."  AR#51063 also talks about this feedback clock and MIO[8].

Cheers,
Mark

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