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Contributor
Contributor
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Registered: ‎04-19-2017

XAPP1305's ps_eth_1g.bsp broken

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Hi all,

 

I tried to follow the XAPP1305 application note for Gigabit Ethernet development on the ZCU102 board.

First of all, I have tried with the PS MIO Ethernet controller. Therefore I downloaded "reference design files" from the link in the XAPP1305, and followed steps in the XAPP1305 Wiki to create a PetaLinux project from available BSPs.

Unfortunately, the ps_eth_1g.bsp seems broken. See the attached image!

 

I am using the PetaLinux 2017.3 as suggested in the XAPP1305 on a Ubuntu machine.

 

Any suggestion/comment would be appreciated.

 

Kind regards,

Khoa

 

 

xapp1305_bsp_broken.PNG
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Contributor
Contributor
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Registered: ‎05-14-2018

Hi,

 

I've had the same problem. I avoided this by just using the BSP for the ZCU102 that can be downloaded from the same page that the 2017.3 PetaLinux installation can be found.

 

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools/archive.html

 

This default BSP boots linux with the 1G interface in the PS running. Which I think is exactly what the ps_eth_1g.bsp should do.

 

Steve.

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Contributor
Contributor
1,547 Views
Registered: ‎05-14-2018

Hi,

 

I've had the same problem. I avoided this by just using the BSP for the ZCU102 that can be downloaded from the same page that the 2017.3 PetaLinux installation can be found.

 

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools/archive.html

 

This default BSP boots linux with the 1G interface in the PS running. Which I think is exactly what the ps_eth_1g.bsp should do.

 

Steve.

View solution in original post

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Explorer
Explorer
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Registered: ‎05-22-2008

I ran into this problem as well.

 

What I'm currently trying to figure out is, when I create a custom HW design what are the steps I need to take in Vivado on the block diagram for the Zynq, as well as the extra steps in the petalinux project, to get 1G Eth from the PS, through the MIO to GEM3 to TI PHY functioning. Starting with a petalinux BSP doesn't really inform this.

 

However, the XAPP1305 PL 10G Eth reference design hardware flow results in a HW design that has both the PS/MIO/GEM3 1G ethernet and PL/axi/xxv_ethernet 10G ethernet. There is another message string:

 

https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/ZCU102-Petalinux-Tutorial-no-BSP/m-p/870964#M18499

 

that I had to follow to get everything working. The output has functioning PS/MIO/GEM3 1G ethernet.  

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