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Registered: ‎09-10-2018

XIP from QSPI and Cache - Zynq-7000 w/o DDR

I have a very simple question which probably has a very complex answer:

If one were to use execute in place (XIP) from QSPI, where the application(s) have a total size less than 512kB (i.e. less than the size of the L2-Cache) and does not interface any external memory such as BRAM or DDR.

After some time, would the application(s) then be fully stored in L2-cache and practically execute from L2-cache?


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Registered: ‎06-27-2017

Hi @ninjanymo ,


My view would be it will be hard to judge that application code will be cached after sometime.

As PC points to QSPI address to fetch the code, L2 can save few parts of the code but not entire. Its good question

Best Regards
Don't forget to reply, kudo, and accept as solution.
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Registered: ‎09-10-2018

I think you are right, it would be hard to judge as it would be very non-deterministic.

The approach used in the XIP and Cache Lock Mode Tech Tip, where the FSBL reads the full application through cache and locks it down seems like the way to go, and I'm working on adapting the method to my own application.

However, I found something interesting in the Zynq-7000's default BSP. The translation_table.s under bsp/ps7_cortexa9_0/libsrc/standalone/src has the following in it's header:

*| Linear QSPI - XIP     | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable    |

However, when I look at how the QSPI region is defined I see this:

.rept	0x0020			/* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
.word	SECT + 0xc0a		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
.set	SECT, SECT+0x100000

When I look at section B3.8 - Memory Region Attributes of the ARM Architecture Reference Manual, I see that TEX[2] == 1 indicates a cachable memory, while TEX[2] == 0 does not.

Am I missing something here or does the header wrongly indicate that the QSPI Flash is set up as cachable memory?

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