cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
575 Views
Registered: ‎09-28-2018

Xilinx 2018.2: SDK JTAG error: no targets found with "name =~"RPU*" && jtag_cable_name

Hi Xilinx,

I'm having difficulties to deploy simple R5 bare metal applications onto the Zynq us+.   ( The OS is a VMware Ubuntu 16.04.1. The SDK is version 2018.2 1.0.0.201806450230 )

I have 2 Digiglent JTAG debuggers, both give back the same error:  

10:35:35 ERROR	: no targets found with "name =~"RPU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A53F7F"". available targets:
  5  PS TAP
     6  PMU
     7  PL
  8  DAP (JTAG port open error. AP transaction error, DAP status 30000021)

The only open project folders are the HW folder, the BSP folder and the C application folder. It compiles like it should but fails upon deployment. 

 

Can you please give some support about this issue?

 

Kind regards

Deville

0 Kudos
3 Replies
Highlighted
Moderator
Moderator
540 Views
Registered: ‎09-12-2007

Re: Xilinx 2018.2: SDK JTAG error: no targets found with "name =~"RPU*" && jtag_cable_name

Can you verify that the boot mode was set to JTAG? if this is set to QSPI, or SD card for example and boot. The bootrom will try seek the boot image from QSPI or SD card. If there is no image it will time out, and the dummy dap will be added

0 Kudos
Highlighted
Explorer
Explorer
531 Views
Registered: ‎09-28-2018

Re: Xilinx 2018.2: SDK JTAG error: no targets found with "name =~"RPU*" && jtag_cable_name

Hi @stephenm 

Yes, they are in JTAG mode. The problem comes and goes.  

Sometimes it helps if I do a hard reset on the evalutation board.  USB3 mode is also activated in the VMware Guest, I saw this coming back on this forum.

 

 

 

0 Kudos
Highlighted
Moderator
Moderator
525 Views
Registered: ‎09-12-2007

Re: Xilinx 2018.2: SDK JTAG error: no targets found with "name =~"RPU*" && jtag_cable_name

Ok, can you try the following.

Can you create a TCL script with the content here:

proc jtag_ctrl {v} {
   set s [jtag seq]
   $s state RESET
   $s irshift -state IDLE -int 12 2084
   $s drshift -state IDLE -int 32 $v
   $s run
   $s delete
}

 

Then launch XSCT, and use the commands:

  • source your_script.tcl
  • connect
  • jtag targets 2
  • jtag_ctrl 3

Note: this is assuming your TAP is at ID 2. The TAP will be the FPGA

For more info on the jtag controller, see the table below:

jtag_cntlr.PNG