We are currently have 3 boards with the Xilinx Zynq Ultrascale+ MPSOC:
FSBL development tool:
OS image development tool for all the boards:
At this stage we still work with JTAG tools (Xilinx probe and Lauterbach) to load both the FSBL and the VXWorks image on the new boards.
We see a failure in the initial stages of the OS startup. The failure happens in the "userRoot" routine. The failure that we see is that the OS code writes to the text section and crushes.
The upper mentioned failures occur in in both new boards in the exact same location.
In the mature board userRoot is completed successfully and the boards starts fine with both configurations (SDK and VITIS).
Can please you advice regarding that behavior?
I recommend to move the post to Embedded Software.