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Registered: ‎03-25-2021

Xilinx Zynq Ultrascale+ MPSOC board bring up issues


We are currently have 3 boards with the Xilinx Zynq Ultrascale+ MPSOC:

  • One mature that is already working with all the capabilities
  • Two in the in initial bring up stages

FSBL development tool:

  • The mature SOC board uses the Xilinx SDK 2018.3 (we also developed a reference FSBL in Xilinx VITIS 2019.2)
  • One new SOC board uses the Xilinx SDK 2018.3
  • Second new SOC uses the Xilinx VITIS 2019.2 for FSBL

OS image development tool for all the boards:

  • Windriver workbench 4 for VxWorks 7 (620) image build.
  • Our VSB is based on the Windriver's supplied sources for the zcu102

At this stage we still work with JTAG tools (Xilinx probe and Lauterbach) to load both the FSBL and the VXWorks image on the new boards.

We see a failure in the initial stages of the OS startup. The failure happens in the "userRoot" routine. The failure that we see is that the OS code writes to the text section and crushes.

  • With our VIP based on the zcu102 we fail in "pmInit" routine (protected memory init)
  • With a  basic VIP created from scratch (profile development) based on the zcu102 we fail in "mmuInit" routine

The upper mentioned failures occur in in both new boards in the exact same location.

In the mature board userRoot is completed successfully and the boards starts fine with both configurations (SDK and VITIS).


Can please you advice regarding that behavior?

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Xilinx Employee
Xilinx Employee
Registered: ‎10-11-2011

I recommend to move the post to Embedded Software.

Don’t forget to reply, kudo, and accept as solution.
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