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Observer ilya.kochub
Observer
1,103 Views
Registered: ‎10-11-2018

ZCU-102 Bare Metal JTAG Debug

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We have two boards ZCU-102  - revision 1.1 both.

I use 2018.3 Vivado and SDK tools.

The project is simple 

project.png

Three applications were created on the same BSP base:

Hello World, Memory Tests and Peripheral Tests.   

We are using JTAG cable and UART cable,  SDK commands are:   

- Xilinx/Program FPGA

-  Debug as/Launch on Hardware (System Debugger) 

On one of ZCU-102 boards - all three tests are working properly.

On another ZCU-102 board only Memory Tests application is working properly.

The other two applications hang up before going to starting point of the application.

We can see  this on XSCT Console of SDK:

Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)

Downloading Program -- C:/Work_Ilya/Viv18_3_prjcts/project_5/project_5.sdk/Perif11/Debug/Perif11.elf
section, .text: 0x00000000 - 0x0000fe93
section, .init: 0x0000fec0 - 0x0000fef3
section, .fini: 0x0000ff00 - 0x0000ff33
section, .note.gnu.build-id: 0x0000ff34 - 0x0000ff57
section, .rodata: 0x0000ff58 - 0x0001186f
section, .rodata1: 0x00011870 - 0x0001187f
section, .sdata2: 0x00011880 - 0x0001187f
section, .sbss2: 0x00011880 - 0x0001187f
section, .data: 0x00011880 - 0x00012f97
section, .data1: 0x00012f98 - 0x00012fbf
section, .ctors: 0x00012fc0 - 0x00012fbf
section, .dtors: 0x00012fc0 - 0x00012fbf
section, .eh_frame: 0x00012fc0 - 0x00012fc3
section, .mmu_tbl0: 0x00013000 - 0x0001300f
section, .mmu_tbl1: 0x00014000 - 0x00015fff
section, .mmu_tbl2: 0x00016000 - 0x00019fff
section, .preinit_array: 0x0001a000 - 0x00019fff
section, .init_array: 0x0001a000 - 0x0001a007
section, .fini_array: 0x0001a008 - 0x0001a047
section, .sdata: 0x0001a048 - 0x0001a07f
section, .sbss: 0x0001a080 - 0x0001a07f
section, .tdata: 0x0001a080 - 0x0001a07f
section, .tbss: 0x0001a080 - 0x0001a07f
section, .bss: 0x0001a080 - 0x0001b6bf
section, .heap: 0x0001b6c0 - 0x0001d6bf
section, .stack: 0x0001d6c0 - 0x000206bf

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Work_Ilya/Viv18_3_prjcts/project_5/project_5.sdk/Perif11/Debug/Perif11.elf
Info: Cortex-A53 #0 (target 9) Running

It was "hang up" example , and the working one is - 

Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)

Downloading Program -- C:/Work_Ilya/Viv18_3_prjcts/project_5/project_5.sdk/Perif11/Debug/Perif11.elf
section, .text: 0x00000000 - 0x0000fe93
section, .init: 0x0000fec0 - 0x0000fef3
section, .fini: 0x0000ff00 - 0x0000ff33
section, .note.gnu.build-id: 0x0000ff34 - 0x0000ff57
section, .rodata: 0x0000ff58 - 0x0001186f
section, .rodata1: 0x00011870 - 0x0001187f
section, .sdata2: 0x00011880 - 0x0001187f
section, .sbss2: 0x00011880 - 0x0001187f
section, .data: 0x00011880 - 0x00012f97
section, .data1: 0x00012f98 - 0x00012fbf
section, .ctors: 0x00012fc0 - 0x00012fbf
section, .dtors: 0x00012fc0 - 0x00012fbf
section, .eh_frame: 0x00012fc0 - 0x00012fc3
section, .mmu_tbl0: 0x00013000 - 0x0001300f
section, .mmu_tbl1: 0x00014000 - 0x00015fff
section, .mmu_tbl2: 0x00016000 - 0x00019fff
section, .preinit_array: 0x0001a000 - 0x00019fff
section, .init_array: 0x0001a000 - 0x0001a007
section, .fini_array: 0x0001a008 - 0x0001a047
section, .sdata: 0x0001a048 - 0x0001a07f
section, .sbss: 0x0001a080 - 0x0001a07f
section, .tdata: 0x0001a080 - 0x0001a07f
section, .tbss: 0x0001a080 - 0x0001a07f
section, .bss: 0x0001a080 - 0x0001b6bf
section, .heap: 0x0001b6c0 - 0x0001d6bf
section, .stack: 0x0001d6c0 - 0x000206bf

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Work_Ilya/Viv18_3_prjcts/project_5/project_5.sdk/Perif11/Debug/Perif11.elf
Info: Cortex-A53 #0 (target 9) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0xdb0 (Breakpoint)
main() at ../src/testperiph.c: 80
80: Xil_ICacheEnable();

 As you can see for this ZCU-102 board - the address

section, .text: 0x00000000 may be the problem,

and for the first one - this address is not a problem at all.

What does it mean - to change the second board for the working one? 

 

 

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
995 Views
Registered: ‎06-13-2018

Re: ZCU-102 Bare Metal JTAG Debug

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Hello @ilya.kochub,

ZCU102 Evaluation Kits labeled 0432055-01 through 0432055-04 are shipped with SODIMM MTA8ATF51264HZ-2G6B1 while ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.

Please follow the workaround mentioned in the AR-71961. You need to change the PCW IP settings according to the new DIMM parameters. 

Capture.PNG

Hope this information will help you.

Regards,

Naveen

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8 Replies
Observer ilya.kochub
Observer
1,097 Views
Registered: ‎10-11-2018

Re: ZCU-102 Bare Metal JTAG Debug

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This is  from XSCT Console of SDK - 

Memory Tests application is working properly on "problem" board:

 

Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)

Downloading Program -- C:/Work_Ilya/Viv18_3_prjcts/project_5/project_5.sdk/Test11/Debug/Test11.elf
section, .text: 0xfffc0000 - 0xfffc3053
section, .init: 0xfffc3080 - 0xfffc30b3
section, .fini: 0xfffc30c0 - 0xfffc30f3
section, .note.gnu.build-id: 0xfffc30f4 - 0xfffc3117
section, .rodata: 0xfffc3118 - 0xfffc34b7
section, .rodata1: 0xfffc34b8 - 0xfffc34bf
section, .sdata2: 0xfffc34c0 - 0xfffc34bf
section, .sbss2: 0xfffc34c0 - 0xfffc34bf
section, .data: 0xfffc34c0 - 0xfffc3df7
section, .data1: 0xfffc3df8 - 0xfffc3dff
section, .ctors: 0xfffc3e00 - 0xfffc3dff
section, .dtors: 0xfffc3e00 - 0xfffc3dff
section, .eh_frame: 0xfffc3e00 - 0xfffc3e03
section, .mmu_tbl0: 0xfffc4000 - 0xfffc400f
section, .mmu_tbl1: 0xfffc5000 - 0xfffc6fff
section, .mmu_tbl2: 0xfffc7000 - 0xfffcafff
section, .preinit_array: 0xfffcb000 - 0xfffcafff
section, .init_array: 0xfffcb000 - 0xfffcb007
section, .fini_array: 0xfffcb008 - 0xfffcb047
section, .sdata: 0xfffcb048 - 0xfffcb07f
section, .sbss: 0xfffcb080 - 0xfffcb07f
section, .tdata: 0xfffcb080 - 0xfffcb07f
section, .tbss: 0xfffcb080 - 0xfffcb07f
section, .bss: 0xfffcb080 - 0xfffcb0ff
section, .heap: 0xfffcb100 - 0xfffcb0ff
section, .stack: 0xfffcb100 - 0xfffce0ff

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0xfffc0000
Successfully downloaded C:/Work_Ilya/Viv18_3_prjcts/project_5/project_5.sdk/Test11/Debug/Test11.elf
Info: Cortex-A53 #0 (target 9) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0xfffc0f44 (Breakpoint)
main() at ../src/memorytest.c: 94
94: init_platform();

 

The address is not 0x00000000 - 

section, .text: 0xfffc0000

 

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Observer ilya.kochub
Observer
1,059 Views
Registered: ‎10-11-2018

Re: ZCU-102 Bare Metal JTAG Debug

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If I change Linker script of "Hello World" application from using DDR to using OCM (0xfffc0000 ... )  - the application is running well.

 "DRAM Diagnostics Test" application shows menu and running well (it's using OCM), but it's stuck/failed on DDR tests.

The meaning is - DDR is not working properly. 

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Xilinx Employee
Xilinx Employee
1,016 Views
Registered: ‎10-11-2011

Re: ZCU-102 Bare Metal JTAG Debug

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Be sure your FSBL is indeed 2018.3 and check if the DDR DIMM is place correctly.

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Xilinx Employee
Xilinx Employee
996 Views
Registered: ‎06-13-2018

Re: ZCU-102 Bare Metal JTAG Debug

Jump to solution

Hello @ilya.kochub,

ZCU102 Evaluation Kits labeled 0432055-01 through 0432055-04 are shipped with SODIMM MTA8ATF51264HZ-2G6B1 while ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.

Please follow the workaround mentioned in the AR-71961. You need to change the PCW IP settings according to the new DIMM parameters. 

Capture.PNG

Hope this information will help you.

Regards,

Naveen

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if the information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------

Visitor yugi_nhc
Visitor
726 Views
Registered: ‎06-27-2018

Re: ZCU-102 Bare Metal JTAG Debug

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I have the same problem when working with simple matrix multiplication example on SDSoC (2018.2)SDSoC.png

My ZCU102 board is revision 1.1 labeled 0432055-05 ~ . 

How can I change the PCW IP settings according to the new DIMM parameters to solve this problem on SDSoC? 

 

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Xilinx Employee
Xilinx Employee
711 Views
Registered: ‎06-13-2018

Re: ZCU-102 Bare Metal JTAG Debug

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Hello @yugi_nhc ,

Can you please let me know which Vivado version you are using? If it is 2018.3 Please check AR-72113. While creating the project on Vivado you need to modify the DDR settings and then you need to generate the DSA file. Please find the below DDR Configuration setting.

Capture.PNG

Regards,

Naveen

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Visitor yugi_nhc
Visitor
696 Views
Registered: ‎06-27-2018

Re: ZCU-102 Bare Metal JTAG Debug

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Hi @nmanitri , I'm using version 2018.2. The project is creating on SDSoC- SDx 2018.2.

Can I modify the DDR settings directly from SDSoC?

Thank you. 

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Xilinx Employee
Xilinx Employee
641 Views
Registered: ‎06-13-2018

Re: ZCU-102 Bare Metal JTAG Debug

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Hello @yugi_nhc,

For this query, I would like to request you please open a new thread. Since this post has already been answered.

Thank you for understanding.

Regards,

Naveen 

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