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Visitor
Visitor
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Registered: ‎01-17-2020

ZCU102: Error when flashing UltraScale+ SF: unrecognized JEDEC id bytes: 10, 35, fe

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Hello,

I'm having a hard time flashing BOOT.bin to the ZCU102. I have set in the block diagram the default QSPI. My guess the problem is in the HDF. I created all the packages (FSBL, PMU, and BSPs) and added in U-Boot which is working on another ZCu102 design and BL31.elf.  When I take another fsbl file from another project the flashing works properly.  Is there something I need to do in the ZCU102 Ultrascale + MPSoC System core block diagram besides enabling QSPI? sf 0 0 0 returns unknown values.  Or, is there something I need to enable in the FSBL?  Another FSBL using the stock ZCU102 board works fine.  What kind of things would prevent QSPI from working?

Command line used: program_flash -f /path/BOOT.bin -fsbl /path/fsbl.elf -flash_type qspi-x8-dual_parallel -blank_check -verify -target_name jsn-XSC0-AAo1BUS+0-24738093-0 -url tcp:aaa.bbb.ccc.ddd:3121

 

 

A bit more background: dip switches are set to boot JTAG, and the source design came from the Zynq Ultrascale+ reboot solution:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841820/Zynq+UltraScale+MPSoC+Restart+solution

I modified this to change from SPI to QSPI and reapplied the  ZCU102 board setting.

 

Best, Josh K

qspi.PNGqspifreq.PNG

qspi-issue.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: ZCU102: Error when flashing UltraScale+ SF: unrecognized JEDEC id bytes: 10, 35, fe

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Can you try with QSPI REF CLOCK in Vivado configured for 200MHz, please?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: ZCU102: Error when flashing UltraScale+ SF: unrecognized JEDEC id bytes: 10, 35, fe

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Can you try with QSPI REF CLOCK in Vivado configured for 200MHz, please?

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Visitor
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Registered: ‎01-17-2020

Re: ZCU102: Error when flashing UltraScale+ SF: unrecognized JEDEC id bytes: 10, 35, fe

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So what's interesting is I started with a fresh ZCU102 project, and the board boots normally.  I was trying to use the following project as a basis:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841820/Zynq+UltraScale+MPSoC+Restart+solution

 

I added in a few devices (GPIO) and I wasn't able to make it bootable.  However a fresh project without this Restart solution booted as expected, so I'm okay closing this issue for now, but will raise it again if I see it.  I will say my current design QSPI is set to 125 MHz as well and it programs / boots.

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