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Visitor
Visitor
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Registered: ‎08-19-2018

ZCU102 baremetall LQSPI access

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Hello, Im trying to manage read/write access to QSPI Flash using LQSPI controller (throw 0xC0000_0000 - 0xDFFF_FFFF linear addess space). I have a simple application for ZCU102 rev1.0, baremetall (Standalone start code + launched psu_init.c via System Debuger in JTAG mode).

0. I have read ug1085 ch24. QSPI.
1. I created an example project for ZCU102 with default setttings.
2. I created new empty Application project (with StandaloneOS boot code)
3. By default QSPI is in GQSPI mode, and access throw linear address space denied. So i turned QSPI to LQSPI mode with follow sequence from ug1085 QSPI System Control : 

Xil_Out32((UINTPTR)(0xFF0F0000+0x00000114),0);    //GQSPI_EN_OFFSET - turn off GQSPI 


Xil_Out32((UINTPTR)(QSPI_BASEADDRESS+LQSPI_CFG_OFFSET),

(
(1<<31)+      //LQSPI Selected
(1<<30)+      //Dual mode
(1<<29)+      //Parallel mode
(0<<28)+      //pages, dont care in this mode
(1<<27)+      //32 bit AXI memory adderess
(0<<16)+      //no IO mode with LQSPI
(0xEB)        //Instruction code Fast read quad I/O (default)
)
);

Xil_Out32((UINTPTR)(0xFF0F0000+0x00000014),1);   //turn on LQSPI

 

 

4. I hope that XPPU dont block QSPI access by default
5. Then i trying to read data from 0хC000_0000 adderess and print value to UART - no responce.
5.1 Im tryed to use Vivado SDK XSCT console command :

xsct% mrd 0xC0000000 0x10
xsct% Memory read error at 0xC0000000. Blocked address 0xC0000000. QSPI access is not allowed


Okay, later, i have read some info about Dual Parallel bit ordering... so may be this is problem. Lets make things more easy.

6. I changed PS QSPI interface settings (via Vivado IDE ) to Sigle x4. Regenerated bitstream, export platform, deleted old one, regenerated BSP with new one.
7. Same actions like 3 - 5 except new LQSPI settings:

Xil_Out32((UINTPTR)(QSPI_BASEADDRESS+LQSPI_CFG_OFFSET),

(
(1<<31)+      //LQSPI Selected
(0<<30)+      //Single mode
(0<<29)+      //bus params, dont care in this mode
(0<<28)+      //pages, dont care in this mode
(1<<27)+      //32 bit AXI memory adderess
(0<<16)+      //no IO mode with LQSPI
(0xEB)        //Instruction code Fast read quad I/O (default)
)
);

 With same results. No data via UART and same respounce via XSTC console.

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Visitor
Visitor
200 Views
Registered: ‎08-19-2018

We switched to single mode. And we try only read operations with LQSPI.

My colleague verified that LQSPI has a problem on the Evolution Borad rev1.0 - he can not read 0xC000_0000 - 0xC000_0010, but it works fine on rev 1.1.

View solution in original post

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Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎10-11-2011

1. Only reads are available in LQSPI

2. Only Single flash for LQSPI

Have you tried C:\Xilinx\2020.1\Vitis\2020.1\data\embeddedsw\XilinxProcessorIPLib\drivers\qspipsu_v1_11\examples\xqspipsu_generic_flash_lqspi_example.c ?

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Visitor
Visitor
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Registered: ‎08-19-2018

We switched to single mode. And we try only read operations with LQSPI.

My colleague verified that LQSPI has a problem on the Evolution Borad rev1.0 - he can not read 0xC000_0000 - 0xC000_0010, but it works fine on rev 1.1.

View solution in original post

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