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Visitor ralfz017
Visitor
1,170 Views
Registered: ‎07-04-2018

ZYNQ JTAG cannot enable PL TAP

Hello,

 

we need to implement boundary scan tests for a chain of 2 XAZU3EG ZYNQs.

This is for manufacturing test - the boards are completely unconfigured

Boot mode is 0000 (JTAG BOOT).

It appears that the devices do not enable the PL TAP - PS TAP only

We can read IDCODE however EXTEST is not possible

 

Tried the JTAG_CTRL (see page 1139 in ug1085) instruction without success

 

What would be the correct Power-Up Reset sequence to get into

full JTAG mode (including PL TAP) ?

 

 

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3 Replies
Xilinx Employee
Xilinx Employee
1,126 Views
Registered: ‎10-11-2011

Re: ZYNQ JTAG cannot enable PL TAP

It's strange, I thought the PL TAP would be there if the PL is properly powered at POR_B release.

Be sure POR_B is released after Tpor to have the PL TAP available.

Also, Could this be it? AR67740.

I found this snippet internally but I didn't have a chance to verify it:

// Load JTAG_CTRL instruction to the Zynq UltraScale+ MPSoC PS TAP instruction register
SIR 12 TDI(83F);
// Set JTAG_CTRL to include both Zynq UltraScale+ MPSoC PS TAP and ARM DAP
// 0x00000001 = PS TAP and DUMMY DAP
// 0x00000003 = PS TAP and ARM DAP
SDR 32 TDI(00000003);
// Reset required to sync the TAPs after the internal JTAG path is reconfigured (above).
// Hold TMS=High for at least 5 TCK cycles
STATE RESET;
STATE IDLE;
STATE RESET;

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Visitor ralfz017
Visitor
1,024 Views
Registered: ‎07-04-2018

Re: ZYNQ JTAG cannot enable PL TAP

Sorry for replying late - unfortunately only now can I return to this project and evaluate the problem again.

Thank you very much for the answer.

According to DS925 TPor is Min.100us.

Actually we assert POR_B low, then we apply power and then we measure all on-board generated voltages. Once all of them are up and stable (and the Clock is stable too) then we assert POR_B high. This actually takes a few 100 ms, so TPor should be OK.

About the JTAG_CTRL command:

We had already tried this but without success.

From what I gather from the datasheet (UG1085 v1.8) page 1144:

In reset and pre-boot stage only IDCODE and BYPASS are available.

This is exactly what we see. No EXTEST.

EXTEST would require the PL TAP in the Chain. And (p1142 Instruction availability) the JTAG_CTRL command is not available at this stage neither.

So how come we are stalled at this stage?

What other requirement must be fulfilled in order for the device to start up correctly?

I gather from p.1174 that a failed LBIST can cause the device to stall - could that be the problem?

There is mention of the JTAG_STATUS command however this is declared private in the BSDL and the JTAG_STATUS register is not defined so we cannot use this.

Would it be possible to provide a BSDL with this enabled so we can try to see what is causing our problems?

I would normally assume that a completely unconfigured device would simply go into normal JTAG mode without any trouble!!

 

 

 

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Xilinx Employee
Xilinx Employee
982 Views
Registered: ‎10-11-2011

Re: ZYNQ JTAG cannot enable PL TAP

On a JTAG boot, PS TAP and PL TAP should be there automatically. so JTAG_CTRL and JTAG_STATUS are available upon a successful boot. These are PS TAP commands (not ARM DAP) and they are defined in the BSDL.

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